74HCT138：标准逻辑
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT138 | 74HCT138.pdf | - | 0 | HCT | 4.5 | 5.5 | - | - | - | - | 35 | 4 |
Description
The 74HCT138 is an high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types. The device accepts a three bit binary weighted address on input pins A0, A1 and A2 and when enab°C will porduce one active low output with the remaing seven being high. There are two active LOW enable inputs 1 and 2, and one active HIGH enable input E3. The disab°C device state results in all outputs being high. The enable state occurs with 1 and 2 asserted low and E3 asserted high. The multiple enable lines allow for the parallel expansion of decoders to create 4-to-16 line versions with no additional parts and 5-to-32 versions with the addition of a single inverter.
Application
- Memory chip select decoding
- Demultiplexing
- Single line peripheral control
- Allow simple serial bit streams from a microcontroller to control as many peripheral lines as needed.
订购型号
- 74HCT138S16-13
- 74HCT138T16-13
SO-16
TSSOP-16
- 74HCT138.pdf 74HCT138
