74LVC125A：标准逻辑
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC125A | 74LVC125A.pdf | - | 4 | LVC | 1.65 | 5.5 | - | 11.8 | 5.8 | 4.6 | - | 24 |
Description
The 74LVC125A provides four independent buffers with three state outputs. Each output is independently control°C by an associated output enable pin (OE) which places the device in the high impedance state when driven high. The device is designed for operation with a power supply range of 1.65V to 5.5V. The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Application
- Voltage Level Shifting
- General Purpose Logic
- Power Down Signal Isolation
- Wide array of products such as: o PCs, networking, notebooks, ultrabooks, netbooks o Computer peripherals, hard drives, CD/DVD ROM o TV, DVD, DVR, set top box
订购型号
- 74LVC125AS14-13
- 74LVC125AT14-13
TSSOP-14
SO-14
- 74LVC125A.pdf 74LVC125A
