The HI3197 is a high-speed D/A converter which can perform the multiplexed input of the two system 10-bit data. The maximum conversion rate achieves 125 MSPS. The multiplexed operation is possible by the 1/2 frequencydivided clock or by halving the frequency of the clock with the clock frequency divider circuit having the reset pin in the IC. The data input is TTL; the clock input pin and reset input pin can select either TTL or PECL according to the application.
Key Features
- Resolution 10 Bits
- Conversion Rate 125 MSPS (PECL) 100 MSPS (TTL)
- Data Input Level TTL
- Low Power Consumption 400mW (Typ)
- Low Glitch Energy 1.5pV;s
- Clock, Reset Input Level: TTL and PECL Compatible 2:1 Multiplexed Input Function
- 1/2 Frequency-Divided Clock Output Possible by the Built- In Clock Frequency Divider Circuit
- Voltage Output (50Ω Load Drive Possible)
- Single Power Supply or ±Dual Power Supplies
- Polarity Switching Function of Reset Signal
Applications
- LCD
- DDS
- HDTV
- Communications (QPSK, QAM)
Datasheets| Title | Type | Updated | Size | Other Languages |
|---|
| HI3197 Datasheet | PDF | 20 Nov 2014 | 222 KB | |
Order Information| Part Number | Package Type | Weight(g) | Pins | MSL Rating | Peak Temp (°C) | RoHS Status |
|---|
|
| HI3197JCQ | Retired - Please contact us for package data | | | | | RoHS |
|
|
