产品特性

• C Compiler Optimized Architecture: Optional extended instruction set designed to optimize re-entrant code
• Optional extended instruction set designed to optimize re-entrant code
• Up to 1024 bytes Data EEPROM
• Up to 64 Kbytes Linear program memory addressing
• Up to 3936 bytes Linear data memory addressing
• Up to 16 MIPS operation
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 31-level, software accessible hardware stack
• 8 x 8 single-cycle hardware multiplier
• Precision 16 MHz internal oscillator block: Factory calibrated to ± 1% Software selectable frequencies range of 31 kHz to 16 MHz 64 MHz performance available using PLL no external components required
• Factory calibrated to ± 1%
• Software selectable frequencies range of 31 kHz to 16 MHz
• 64 MHz performance available using PLL
• no external components required
• Four crystal modes up to 64 MHz
• Two external clock modes up to 64 MHz
• 4X Phase Lock Loop (PLL)
• Secondary oscillator using Timer1 @ 32 kHz
• Fail-Safe Clock Monitor: Allows for safe shutdown if peripheral clock stops Two-Speed Oscillator Start-up
• Allows for safe shutdown if peripheral clock stops
• Two-Speed Oscillator Start-up
• Operating Voltage Range: 1.8V to 3.6V
• Self-Programmable under Software Control
• Programmable 16-Level High/Low-Voltage Detection (HLVD) module: Interrupt on High/Low-Voltage Detection
• Interrupt on High/Low-Voltage Detection
• Programmable Brown-out Reset (BOR): With software enable option
• With software enable option
• Extended Watchdog Timer (WDT): Programmable period from 4 ms to 131s
• Programmable period from 4 ms to 131s
• Single-Supply 3V In-Circuit Serial Programming™ (ICSP™) via two pins
• In-Circuit Debug (ICD) via Two Pins
• Sleep mode: 100 nA
• Watchdog Timer: 500 nA
• Timer1 Oscillator: 500 nA @ 32 kHz
• Analog-to-Digital Converter (ADC) module : 10-bit resolution, 13 External Channels Auto-acquisition capability Conversion available during Sleep 1.2V Fixed Voltage Reference (FVR) channel Independent input multiplexing
• 10-bit resolution, 13 External Channels
• Auto-acquisition capability
• Conversion available during Sleep
• 1.2V Fixed Voltage Reference (FVR) channel
• Independent input multiplexing
• Analog Comparator module: Two rail-to-rail analog comparators Independent input multiplexing
• Two rail-to-rail analog comparators
• Independent input multiplexing
• Voltage Reference (CVREF) module Programmable (% VDD), 16 steps Two 16-level voltage ranges using VREF pins
• Programmable (% VDD), 16 steps
• Two 16-level voltage ranges using VREF pins
• Up to 35 I/O pins plus 1 input-only pin: High-Current Sink/Source 25 mA/25 mA Three programmable external interrupts Four programmable interrupt-on-change Eight programmable weak pull-ups Programmable slew rate
• High-Current Sink/Source 25 mA/25 mA
• Three programmable external interrupts
• Four programmable interrupt-on-change
• Eight programmable weak pull-ups
• Programmable slew rate
• Capture/Compare/PWM (CCP) module
• Enhanced CCP (ECCP) module: One, two or four PWM outputs Selectable polarity Programmable dead time Auto-Shutdown and Auto-Restart
• One, two or four PWM outputs
• Selectable polarity
• Programmable dead time
• Auto-Shutdown and Auto-Restart
• Master Synchronous Serial Port (MSSP) module 3-wire SPI (supports all 4 modes) I2C™ Master and Slave modes with address mask
• 3-wire SPI (supports all 4 modes)
• I2C™ Master and Slave modes with address mask
• Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module: Supports RS-485, RS-232 and LIN RS-232 operation using internal oscillator Auto-Wake-up on Break Auto-Baud Detect
• Supports RS-485, RS-232 and LIN
• RS-232 operation using internal oscillator
• Auto-Wake-up on Break
• Auto-Baud Detect

技术参数