产品特性

• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Internal Oscillator: 96 MHz PLL option Multiple clock divide options Run-time self-calibration capability for maintaining better than ±0.20% accuracy Fast start-up
• 96 MHz PLL option
• Multiple clock divide options
• Run-time self-calibration capability for maintaining better than ±0.20% accuracy
• Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read and Write Addressing of Data Memory
• 10/12-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter: 12-bit conversion rate of 200 ksps Auto-scan and threshold compare features Conversion available during Sleep
• 12-bit conversion rate of 200 ksps
• Auto-scan and threshold compare features
• Conversion available during Sleep
• Three Rail-to-Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
• Charge Time Measurement Unit (CTMU): Used for capacitive touch sensing, up to 24 channels Time measurement down to 100 ps resolution
• Used for capacitive touch sensing, up to 24 channels
• Time measurement down to 100 ps resolution
• Capable of Holding Two Independent Software Applications, including Bootloader
• Permits Simultaneous Programming of One Partition while Executing Application Code from the Other
• Allows Run-Time Switching Between Active Partitions
• Sleep and Idle modes Selectively Shut Down Peripherals and/or Core for Substantial Power Reduction and Fast Wake-up
• Doze mode Allows CPU to Run at a Lower Clock Speed than Peripherals
• Alternate Clock modes Allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• Wide Range Digitally Controlled Oscillator (DCO) for Fast Start-up and Low-Power Operation

技术参数