产品特性

• 16-bit Sigma-Delta ADC (2 diff. ch)
• 12-bit 10MSPS Pipeline ADC (30 ch)
• 2x10-bit 1MSPS DAC
• 2 Operational Amplifiers
• 3 Comparators
• 3 Voltage References
• Charge Time Measurement Unit (CTMU)
• 18 nA Deep Sleep mode
• 350 nA RTCC in Vbat mode
• 380 nA Low Voltage Sleep mode (RAM retention)
• 400 nA Real Time Clock & Calendar operation in Sleep modes
• 240 nA Watch Dog Timer operation in Deep Sleep modes
• 180 µA/MHz Run mode
• Power Modes: Run, Doze, Idle, Sleep, Low Voltage Sleep, Deep Sleep, Vbat
• Multiple, flexible clock modes for optimum performance and power management
• Deep Sleep Wake Sources: DSBOR, DSWDT, INT0 and RTCC
• Up to 16 MIPS performance
• Single Cycle Instruction Execution
• 16 x 16 Hardware Multiply, & 32-bit x 16-bit Hardware Divider
• C Compiler Optimized Instruction Set Architecture
• 6 Channel DMA
• USB with Device/Host/OTG support
• Segmented LCD driver with charge-pump, 31 seg. x 8 comm.
• Peripheral Pin Select allows I/O remapping of many peripherals in real time
• Hardware RTCC, Real-Time Clock Calendar with alarm system
• Internal oscillators support - 31 kHz to 8 MHz, up to 32 MHz with 4X PLL
• Fail-Safe Clock Monitor - allows safe shutdown if clock fails
• Watchdog Timer with separate RC oscillator
• System Supervisors: Low Power BOR, WDT, INT0 and RTCC
• JTAG Boundary Scan

技术参数