74LVC1G11GS: 单路3输入与门

74LVC1G11提供一个单路3输入与门。

输入可通过3.3 V或5 V器件进行驱动。该特性允许在混合3.3 V和5 V环境中使用该器件。

所有输入处的施密特触发器动作使电路高度容许较慢的输入上升和下降时间。

该器件完全适合使用IOFF的局部掉电应用。IOFF电路可禁用输出,防止掉电时破坏性回流电流通过该器件。

sot1202_3d
数据手册 (1)
名称/描述Modified Date
Single 3-input AND gate (REV 8.0) PDF (201.0 kB) 74LVC1G11 [English]17 Sep 2015
应用说明 (3)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
MicroPak soldering information (REV 2.0) PDF (245.0 kB) AN10343 [English]30 Dec 2010
封装信息 (1)
名称/描述Modified Date
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm (REV 1.0) PDF (192.0 kB) SOT1202 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
Reversed product orientation 12NC ending 132 (REV 2.0) PDF (92.0 kB) SOT1202_132 [English]04 Apr 2013
支持信息 (1)
名称/描述Modified Date
MAR_SOT1202 Topmark (REV 1.0) PDF (49.0 kB) MAR_SOT1202 [English]03 Jun 2013
IBIS
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明类型Output drive capability (mA)Package versiontpd (ns)fmax (MHz)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC1G11GSActiveLVC1.65 - 5.5AND gatesCMOS / LVTTLsingle 3-input AND gateAND gates+/- 32SOT12022.61751low-40~12533733.5228XSON66
Single 3-input AND gate 74LVC1G11GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
MicroPak soldering information NTS0102_Q100
XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm NCX2200GS
Reversed product orientation 12NC ending 132 NTS0101
MAR_SOT1202 Topmark NCX2200GS
74LVC1G11 IBIS model 74LVC1G11GW
74LVC2G17