NB3N1200K: 3.3 V 100/133 MHz Differential 1:12 HCSL Clock ZDB/Fanout Buffer for PCle

The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1200K and NB3W1200L utilize pseudo−external feedback topology to achieve low input−to output delay variation. The NB3N1200K is configured with the HCSL buffer type, while the NB3W1200L is configured with the low−power NMOS Push−Pull buffer type.

特性
  • 12 Differential Clock Output Pairs @ 0.7 V
  • HCSL Compatible Outputs for NB3N1200K
  • Optimized 100 MHz and 133 MHz Operating Frequencies to Meet The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
  • DB1200Z Compliant
  • 3.3 V ±5% Supply Voltage Operation
  • Fixed−Feedback for Lowest Input−To−Output Delay Variation
  • SMBus Programmable Configurations to Allow Multiple Buffers in aSingle Control Network
  • PLL Bypass Configurable for PLL or Fanout Operation
  • Programmable PLL Bandwidth
  • 2 Tri−level Addresses Selection (9 SMBUS Addresses)
  • Individual OE Control Pin for Each of 12 Outputs
  • Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
  • 50 ps Max Output−to−Output Skew Performance
  • 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
  • 100 ps Input to Output Delay Variation Performance
  • QFN 64−pin Package, 9 mm x 9 mm
  • Spread Spectrum Compatible: Tracks Input Clock Spreading for Low EMI
  • 0°C to +70°C Ambient Operating Temperature
应用
  • Industrial
  • Networking
  • Computing
  • Consumer
终端产品
  • Desktop
  • Notebook
  • Switchers/Routers
  • Servers
  • Set Top Box
  • Automated Test Equipment
软件 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N1200KMNGEVB SoftwareNB3N1200KMNGEVB_SOFTWARE (11132kB)1
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V 100/133 MHz Differential 1:12 HCSL Clock Fanout Buffer for PCIeNB3N1200K/D (174kB)2
应用注释 (1)
Document TitleDocument ID/SizeRevisionRevision Date
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing ChallengesAND9202/D (179kB)1Mar, 2015
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN64 9x9, 0.5P (PUNCH & SAWN)485DH (62.1kB)O
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N1200K IBIS ModelNB3N1200K.ibs (70kB)3.1Jun, 2013
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3N1200K/NB3W1200L Evaluation Board User's ManualEVBUM2216/D (792kB)0Dec, 2013
评估板与开发工具
产品状况Compliance简短说明
NB3N1200KMNGEVBActivePb-freeStandard HCSL Output Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB3N1200KMNGActivePb-free Halide freeQFN-64485DH3Tray JEDEC260联系BDTIC
NB3N1200KMNTXGActivePb-free Halide freeQFN-64485DH3Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3N1200KMNGBuffer11:12HCSLHCSL3.30.04 0.002 0.00150087.5133.33 100
NB3N1200KMNTXGBuffer11:12HCSLHCSL3.30.04 0.001 0.00250087.5133.33 100
3.3 V 100/133 MHz Differential 1:12 HCSL Clock Fanout Buffer for PCIe (174kB) NB3N1200K
NB3N1200KMNGEVB SOFTWARE - 11132 KB NB3N1200KMNGEVB
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges NCN2612B
NB3N1200K IBIS Model NB3N1200K
EVBUM2216/D - 792 KB NB3N1200KMNGEVB
QFN64 9x9, 0.5P (PUNCH & SAWN) NB3N1200K