NB3N1200K: 3.3 V 100/133 MHz Differential 1:12 HCSL Clock ZDB/Fanout Buffer for PCle
The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
distributing the reference clocks for Intel® QuickPath Interconnect
(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable
Memory Interconnect (Intel SMI) applications. The VCO of the
device is optimized to support 100 MHz and 133 MHz frequency
operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power NMOS Push−Pull buffer type.
Features- 12 Differential Clock Output Pairs @ 0.7 V
- HCSL Compatible Outputs for NB3N1200K
- Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
- DB1200Z Compliant
- 3.3 V ±5% Supply Voltage Operation
- Fixed−Feedback for Lowest Input−To−Output Delay Variation
- SMBus Programmable Configurations to Allow Multiple Buffers in aSingle Control Network
- PLL Bypass Configurable for PLL or Fanout Operation
- Programmable PLL Bandwidth
- 2 Tri−level Addresses Selection (9 SMBUS Addresses)
- Individual OE Control Pin for Each of 12 Outputs
- Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
- 50 ps Max Output−to−Output Skew Performance
- 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
- 100 ps Input to Output Delay Variation Performance
- QFN 64−pin Package, 9 mm x 9 mm
- Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
EMI
- 0°C to +70°C Ambient Operating Temperature
|
Applications- Industrial
- Networking
- Computing
- Consumer
| End Products- Desktop
- Notebook
- Switchers/Routers
- Servers
- Set Top Box
- Automated Test Equipment
|
Software (1)
Data Sheets (1)
Application Notes (1)
Package Drawings (1)
Simulation Models (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|
| NB3N1200K IBIS Model | NB3N1200K.ibs (70kB) | 3.1 | Jun, 2013 |
Evaluation Board Documents (1)
Evaluation/Development Tool Information
| Product | Status | Compliance | Short Description |
|---|
| NB3N1200KMNGEVB | Active | Pb-free | Standard HCSL Output Evaluation Board |
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| NB3N1200KMNG | Active | Pb-free
Halide free | QFN-64 | 485DH | 3 | Tray JEDEC | 260 | Contact BDTIC |
| NB3N1200KMNTXG | Active | Pb-free
Halide free | QFN-64 | 485DH | 3 | Tape and Reel | 1000 | Contact BDTIC |
Specifications
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB3N1200KMNG | Buffer | 1 | 1:12 | HCSL | HCSL | 3.3 | 0.04
0.002
0.001 | 50 | 0 | 87.5 | 133.33
100 | |
| NB3N1200KMNTXG | Buffer | 1 | 1:12 | HCSL | HCSL | 3.3 | 0.04
0.001
0.002 | 50 | 0 | 87.5 | 133.33
100 | |
