NBSG16M: Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer

The NBSG16M is a differential current mode logic (CML) receiver/driver. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.Inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 Ω source termination resistor to VCC. The device generates 400 mV output amplitude with 50 Ω receiver resistor to VCC.The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.

特性
  • Maximum Input Clock Frequency > 10 GHz Typical
  • Maximum Input Data Rate > 10 Gb/s Typical
  • 120 ps Typical Propagation Delay
  • 35 ps Typical Rise and Fall Times
  • Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • CML Output Level; 400 mV Peak-to-Peak Output with 50 _ Receiver Resistor to VCC
  • 50 Ω Internal Input and Output Termination Resistors
  • Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices
  • VBB Reference Voltage Output
  • Pb-Free Packages are Available
应用
  • Backplane buffering
  • OC-3 through OC-192 clock or data distribution/driver
  • Gigabit Ethernet clock or data driver
  • Fibre Channel distribution/driver
封装
应用注释 (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Chips that RipAND8068/D (25.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output StructureAND8173/D (144.0kB)3
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nbsg16m at 3.3VNBSG16M_33V.IBS (28.0kB)3
评估板文档 (1)
Document TitleDocument ID/SizeRevisionRevision Date
NBSG16MMNEVB ManualEVBUM2095/D (180.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator BufferNBSG16M/D (137kB)9Jun, 2014
评估板与开发工具
产品状况Compliance简短说明
NBSG16MMNEVBActiveNBSG16M 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer Evaluation Board
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NBSG16MMNGActivePb-free Halide freeQFN-16485G-011Tube123联系BDTIC
NBSG16MMNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NBSG16MMNGSignal Driver11:1LVDS CMOS CML ECL TTLCML2.5 3.30.20.12531000010000
NBSG16MMNR2GSignal Driver11:1CMOS LVDS CML ECL TTLCML3.3 2.50.20.12531000010000
2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer (137kB) NBSG16M
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Chips that Rip NBSG86A
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure NB6L295M
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for nbsg16m at 3.3V NBSG16M
EVBUM2095/D - 180 NBSG16MMNEVB
QFN16, 3x3, 0.5P NLSF308