NBSG16M: Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer
The NBSG16M is a differential current mode logic (CML) receiver/driver. The device is functionally equivalent to the EP16, LVEP16, or SG16 devices with CML output structure and lower EMI capabilities.Inputs incorporate internal 50 Ω termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. The CML output structure contains internal 50 Ω source termination resistor to VCC. The device generates 400 mV output amplitude with 50 Ω receiver resistor to VCC.The VBB pin is internally generated voltage supply available to this device only. For all single−ended input conditions, the unused complementary differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB output should be left open.
Features- Maximum Input Clock Frequency > 10 GHz Typical
- Maximum Input Data Rate > 10 Gb/s Typical
- 120 ps Typical Propagation Delay
- 35 ps Typical Rise and Fall Times
- Positive CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
- Negative CML Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
- CML Output Level; 400 mV Peak-to-Peak Output with 50 _ Receiver Resistor to VCC
- 50 Ω Internal Input and Output Termination Resistors
- Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL and SG Devices
- VBB Reference Voltage Output
- Pb-Free Packages are Available
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Applications- Backplane buffering
- OC-3 through OC-192 clock or data distribution/driver
- Gigabit Ethernet clock or data driver
- Fibre Channel distribution/driver
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Application Notes (12)
Package Drawings (1)
Simulation Models (1)
Evaluation Board Documents (1)
Data Sheets (1)
Evaluation/Development Tool Information
| Product | Status | Compliance | Short Description |
|---|
| NBSG16MMNEVB | Active | | NBSG16M 2.5 V/3.3 V Multilevel Input to CML Clock/Data Receiver/ Driver/Translator Buffer Evaluation Board |
Order Information
| Product | Status | Compliance | Package | MSL* | Container | Budgetary Price/Unit |
|---|
| NBSG16MMNG | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tube | 123 | Contact BDTIC |
| NBSG16MMNR2G | Active | Pb-free
Halide free | QFN-16 | 485G-01 | 1 | Tape and Reel | 3000 | Contact BDTIC |
Specifications
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NBSG16MMNG | Signal Driver | 1 | 1:1 | LVDS
CMOS
CML
ECL
TTL | CML | 2.5
3.3 | 0.2 | | 0.12 | 53 | 10000 | 10000 |
| NBSG16MMNR2G | Signal Driver | 1 | 1:1 | CMOS
LVDS
CML
ECL
TTL | CML | 3.3
2.5 | 0.2 | | 0.12 | 53 | 10000 | 10000 |
