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ISP1763A：Hi-Speed USB OTG controller for portable applications

The ISP1763A is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced slave host controller and the ISP1582 peripheral controller.

The Hi-Speed USB host controller and peripheral controller comply with Universal Serial Bus Specification Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The Enhanced Host Controller Interface (EHCI) core implemented in the host controller is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB Specification Rev. 1.3.

The ISP1763A has two USB ports. Port 1 can be configured to function as a downstream port, an upstream port, or as an OTG port; port 2 is always configured as a downstream port. Port 2 supports Session Request Protocol (SRP) detection from the B-device. The OTG port supports Host Negotiation Protocol (HNP) and SRP as specified in On-The-Go Supplement to the USB Specification Rev. 1.3.

The ISP1763A support multiple bus interfaces with 8-bit or 16-bit bus. The ISP1763A can interface to processors with digital I/O voltages of 1.8 V or 3.3 V.

Key Features

• Compliant with:
  • Universal Serial Bus Specification Rev. 2.0
  • On-The-Go Supplement to the USB Specification Rev. 1.3
• Small form-factor for portable applications; available in VFQFPN64 and TFBGA64 Restriction of Hazardous Substances (RoHS) compliant, halogen-free and lead-free packages
• Low power consumption for portable applications
• Host supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s); supports disabling of high-speed mode on each port
• Peripheral supports data transfer at high-speed (480 Mbit/s) and full-speed (12 Mbit/s)
• Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed) support
• Two USB ports:
  • Port 1: OTG, host, or peripheral port
  • Port 2: Host port only (supports SRP detection)
• Supports OTG HNP and SRP
• Supports 8-bit or 16-bit CPU bus interface
• Flexibility to interface with various types of processors:
  • NOR Flash interface (multiplexed mode)
  • NAND Flash interface (multiplexed mode)
  • General multiplex interface
  • SRAM interface
• Single configurable interrupt (INT) line for the host controller, peripheral controller, and OTG controller
• Integrated Phase-Locked Loop (PLL) supports external 12 MHz, 19.2 MHz, and 24 MHz crystal, and direct clock source
• Supports remote wake-up from deep sleep mode
• Supports interfacing I/O voltage of 1.8 V or 3.3 V; separate I/O voltage supply pins minimize crosstalk
• Internal voltage regulator supplies 1.2 V to the digital core
• 3.0 V to 3.6 V supply voltage input range for the internal USB transceiver
• Supports hybrid power mode; VCC(3V3) is not present, VCC(I/O) is powered
• Host controller-specific features:
  • EHCI core is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0
  • Integrated TT for Original USB device support on both the ports
  • Integrated 24 kB high-speed memory
  • Power switching and over-current reporting on per-port basis
• Peripheral controller-specific features:
  • Compliant with Universal Serial Bus Specification Rev. 2.0
  • Integrated 4 kB memory to support seven IN endpoints, seven OUT endpoints, and one fixed control IN/OUT endpoint
  • VBUS detection in deep sleep mode
• OTG controller-specific features:
  • Supports OTG HNP and SRP using status and control registers for the software implementation in OTG dual-role devices
  • Integrated VBUS voltage comparators
  • Integrated cable (ID) detector
• Programmable timers with high resolution (0.01 ms to 80 ms)

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