AD9511 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs

The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Three independent LVPECL and two LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz.

The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.

The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.

Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. One output also features a programmable delay element with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.

The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.

The AD9511 is available in a 48-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.

Applications

Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ Converters
Wireless infrastructure transceivers
High performance instrumentation
Broadband infrastructure

Features and Benefits

Phase locked loop (PLL) Core
Reference input frequencies to 250 MHz
Programmable dual-modulus prescaler
Programmable charge pump (CP) current
Separate CP supply (VCP) extends tuning range
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust

Three independent 1.2 GHz LVPECL outputs
Additive output jitter , 225 fs RMS
Two independent 800 MHz/250 MHz LVDS/CMOS outputs
Additive output jitter, 275 fs RMS
Fine delay adjust on one output, 5-bit delay words
4-wire or 3-wire serial control port
Space-saving 48-lead LFCSP

Data Sheets

Document	note
AD9511: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs Data Sheet (Rev. A)	PDF 1187 kB

Application Notes

Document	note
AN-0974: Multicarrier TD-SCMA Feasibility	PDF 634 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)	PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)	PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)	PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)	PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)	PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)	PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB