AD9515 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs

The AD9515 features a two-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are two independent clock outputs. One output is LVPECL, while the other output can be set to either LVDS or CMOS levels. The LVPECL output operates to 1.6 GHz. The other output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.

The AD9515 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.

The AD9515 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9515 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Applications

Low jitter, low phase noise clock distribution
Clocking high speed ADC, DAC, DDS, DDC, DUC, MxFE
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE

Features and Benefits

1.6 GHz differential clock input
2 programmable dividers, in range from 1 to 32
Phase select for output-to-output coarse delay adjust
1.6 GHz LVPECL clock output
LVPECL Additive output jitter 225 fs rms

800 MHz/250 MHz LVDS/CMOS clock output
LVDS/CMOS Additive output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP

Data Sheets

Document	note
AD9515: 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs Data Sheet (Rev. A)	PDF 650 kB

Application Notes

Document	note
AN-0974: Multicarrier TD-SCMA Feasibility	PDF 634 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)	PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)	PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)	PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)	PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)	PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)	PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB