AD9548 Quad/Octal Input Network Clock Generator/Synchronizer

The AD9548 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9548 generates an output clock synchronized to one of up to four differential or eight single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9548 continuously generates a clean (low jitter), valid output clock even when all references have failed by means of a digitally controlled loop and holdover circuitry.

The AD9548 operates over an industrial temperature range of −40°C to +85°C.

Applications
  • Network synchronization
  • Cleanup of reference clock jitter
  • GPS 1 pulse per second synchronization
  • SONET/SDH clocks up to OC-192, including FEC
  • Stratum 2 holdover, jitter cleanup, and phase transient control
  • Stratum 3E and Stratum 3 reference clocks
  • Wireless base stations, controllers
  • Cable infrastructure
  • Data communications
Features and Benefits
  • Supports Stratum2 stability in holdover mode
  • Supports reference switchover with phase build-out
  • Supports hitless reference switchover
  • Auto/manual holdover and reference switchover
  • 4 pairs of reference input pins with each pair configurable as a single differential input or as 2 independent single-ended inputs
  • Input reference frequencies from 1 Hz to 750 MHz
  • Reference validation and frequency monitoring (1ppm)
  • Programmable input reference switchover priority
  • Please see data sheet for additional features.
    • Clock & Timing
    RF & Microwave
    AD9548 IBIS Models
    Data Sheets
    Documentnote
    AD9548: Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet (Rev. G)PDF 1870 kB
    Application Notes
    Documentnote
    AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications (Rev. A)PDF 210 kB
    AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter (Rev. 0)PDF 470 kB
    AN-1064: Understanding the Input Reference Monitors of the AD9548 (Rev. 0)PDF 155 kB
    AN-1002: The AD9548 as a GPS Disciplined Stratum 2 Clock (Rev. 0)PDF 157 kB
    User Guides
    Documentnote
    UG-639: Evaluating the AD9547 and AD9548 Digital PLL Clock SynthesizersPDF 931 kB
    Frequently Asked Questions
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    AD9548BCPZ Production88 ld LFCSP (12x12mm w/6.0mm pad) OTH 168-40 to 85C26.5722.59Y
    AD9548BCPZ-REEL7 Production88 ld LFCSP (12x12mm w/6.0mm pad) REEL 400-40 to 85C26.5722.59Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    AD9548/PCBZEvaluation Board250Y
    Reference Materials
    AD9548: Quad/Octal Input Network Clock Generator/Synchronizer Data Sheet (Rev. G) ad9548
    AD9548 (All Models/All Speed Grades) ad9548
    AN-1079: Determining the Maximum Tolerable Frequency Drift Rate of the AD9548 System Clock in Low Loop Bandwidth Applications (R ad9548
    AN-1079: 确定AD9548系统时钟低环路带宽应用中的最大容许频率漂移速率 (Rev. 0) ad9548
    AN-1061: Behavior of the AD9548 Phase and Frequency Lock Detectors in the Presence of Random Jitter (Rev. 0) ad9548
    AN-1064: Understanding the Input Reference Monitors of the AD9548 (Rev. 0) ad9548
    AN-1064：了解AD9548的输入基准监控器 (Rev. 0) ad9548
    AN-1061：存在随机抖动时鉴频鉴相器AD9548的特性 (Rev. 0) ad9548
    AN-1002: The AD9548 as a GPS Disciplined Stratum 2 Clock (Rev. 0) ad9548
    AN-1002: AD9548用作GPS可驯Stratum 2时钟 (Rev. 0) ad9548
    UG-639: Evaluating the AD9547 and AD9548 Digital PLL Clock Synthesizers ad9548
    RF Source Booklet adf9010
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