ADF4196 Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer
The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is
specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the
ADF4196 suitable for pulse Doppler radar applications.
The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.
A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.
Applications
- GSM/EDGE base stations
- PHS base stations
- Pulsed Doppler radar
- Instrumentation and test equipment
- Beam-forming/phased array systems
Features and BenefitsFast settling, fractional-N
PLL architectureSingle PLL replaces ping-pong synthesizersFrequency hop across GSM band in 5 μs with phase settled within 20 μs1 degree rms phase error at
4 GHz RF outputDigitally programmable output phaseRF input range up to 6 GHz3-wire serial interfaceOn-chip, low noise differential amplifierPhase noise figure of merit: –216 dBc/Hz | Aerospace and Defense |
Data Sheets
Application Notes
User Guides
Order Information
Part Number | Package | Packing Qty | Temp Range | Price 100-499 | Price 1000+ | RoHS |
---|
ADF4196BCPZ Production | 32 ld LFCSP (5x5mm) w/3.1mm exposed pad | OTH 490 | -40 to 85C | 10.11 | 9.35 | Y |
ADF4196BCPZ-RL7 Production | 32 ld LFCSP (5x5mm) w/3.1mm exposed pad | REEL 1500 | -40 to 85C | 0 | 9.35 | Y |
Evaluation Boards
Part Number | Description | Price | RoHS |
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EV-ADF4196SD1Z | Evaluation Board (No VCO or Loop Filter) | 141 | Y |
EVAL-SDP-CS1Z | SDP-S Controller Board - Interface to EV-ADF4196SD1Z (also required) | 49 | Y |
Reference Materials