ADF4196 Low Phase Noise, Fast Settling 6 GHz PLL Frequency Synthesizer

The ADF4196 frequency synthesizer can be used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and transmitters. Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations, and the fast settling feature makes the ADF4196 suitable for pulse Doppler radar applications.

The ADF4196 consists of a low noise, digital phase frequency detector (PFD) and a precision differential charge pump. A differential amplifier converts the differential charge pump output to a single-ended voltage for the external voltage controlled oscillator (VCO). The sigma-delta (Σ-Δ) based fractional interpolator, working with the N divider, allows programmable modulus fractional-N division. Additionally, the 4-bit reference (R) counter and on-chip frequency doubler allow selectable reference signal (REFIN) frequencies at the PFD input.

A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a VCO. The switching architecture ensures that the PLL settles within the GSM time slot guard period, removing the need for a second PLL and associated isolation switches. This decreases the cost, complexity, PCB area, shielding, and characterization found on previous ping-pong GSM PLL architectures.

Applications
  • GSM/EDGE base stations
  • PHS base stations
  • Pulsed Doppler radar
  • Instrumentation and test equipment
  • Beam-forming/phased array systems
Features and Benefits
  • Fast settling, fractional-N
    PLL architecture
  • Single PLL replaces ping-pong synthesizers
  • Frequency hop across GSM band in 5 μs with phase settled within 20 μs
  • 1 degree rms phase error at 4 GHz RF output
  • Digitally programmable output phase
  • RF input range up to 6 GHz
  • 3-wire serial interface
  • On-chip, low noise differential amplifier
  • Phase noise figure of merit: –216 dBc/Hz
  • RF & Microwave
    Aerospace and Defense
    • Solutions
    Data Sheets
    Documentnote
    ADF4196: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer Data Sheet (Rev. D)PDF 2801 kB
    Application Notes
    Documentnote
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
    User Guides
    Documentnote
    UG-476: PLL Software Installation GuidePDF 520 kB
    UG-536: Evaluating the ADF4193 and ADF4196 Frequency Synthesizers for Phase-Locked LoopsPDF 443 kB
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    ADF4196BCPZ Production32 ld LFCSP (5x5mm) w/3.1mm exposed padOTH 490-40 to 85C10.119.35Y
    ADF4196BCPZ-RL7 Production32 ld LFCSP (5x5mm) w/3.1mm exposed padREEL 1500-40 to 85C09.35Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    EV-ADF4196SD1ZEvaluation Board (No VCO or Loop Filter)141Y
    EVAL-SDP-CS1ZSDP-S Controller Board - Interface to EV-ADF4196SD1Z (also required)49Y
    Reference Materials
    ADF4196: Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer Data Sheet (Rev. D) adf4196
    AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
    UG-476: PLL Software Installation Guide adf9010
    UG-476:PLL软件安装指南 adf4360-1
    UG-536: Evaluating the ADF4193 and ADF4196 Frequency Synthesizers for Phase-Locked Loops adf4193
    RF Source Booklet adf9010