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Home > Fairchild Semiconductor > FET > FDZ1905PZ

FDZ1905PZ: -20V Common Drain P-Channel 1.5V PowerTrench® WL-CSP MOSFET

This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. It features two common drain P-channel MOSFETs, which enables bidirectional current flow, on Fairchild's advanced 1.5V PowerTrench® process with state of the art ¡°low pitch¡± WL-CSP packaging process, the FDZ1905PZ minimizes both PCB space and rS1S2(on). This advanced WL-CSP MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, ultra-low profile packaging, low gate charge, and low rS1S2(on).

FDZ1905PZ Datasheet
Features
  • Max rS1S2(on) = 126mΩ at VGS = -4.5V, IS1S2 = -1A
  • Max rS1S2(on) = 141mΩ at VGS = -2.5V, IS1S2 = -1A
  • Max rS1S2(on) = 198mΩ at VGS = -1.8V, IS1S2 = -1A
  • Max rS1S2(on) = 303mΩ at VGS = -1.5V, IS1S2 = -1A
  • Occupies only 1.5 mm² of PCB area, less than 50% of the area of 2 x 2 BGA
  • Ultra-thin package: less than 0.65 mm height when mounted to PCB
  • High power and current handling capability
  • HBM ESD protection level > 4kV (Note 3)
  • RoHS compliant
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
FDZ1905PZFull Production Green as of Mar 2014  China RoHS$0.3289WL-CSP 6L  -  0.625 x 0 x 0mm,  TAPE REEL
  • WL-CSP 6L  Drawing Last Update: Oct 2015
  • WLCSP 2X3 Array Tape And Reel Packing Drawing Last Update: Nov 2016
  • WLCSP 1.0x1.5, Packing Drawing Last Update: Jan 2016
  • WLCSP, Packing Drawing Last Update: Jul 2015
  • WLCSP Tape and Reel Packing Drawing Last Update: Jun 2016
Line 1&Y (Binary Calendar Year Coding)

Line 2&E (Space)
5&X

Line 3&. (Pin One)

Application Notes
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • FDZ1905PZ.pdf
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    WL-CSP 6L  Drawing Last Update: Oct 2015
    WLCSP 2X3 Array Tape And Reel Packing Drawing Last Update: Nov 2016
    WLCSP 1.0x1.5, Packing Drawing Last Update: Jan 2016
    WLCSP, Packing Drawing Last Update: Jul 2015
    WLCSP Tape and Reel Packing Drawing Last Update: Jun 2016
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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