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LTC3831 - High Power Synchronous Switching Regulator Controller for DDR Memory Termination

The LTC3831 is a high power, high efficiency switching regulator controller designed for DDR memory termination. The LTC3831 generates an output voltage equal to 1/2 of an external supply or reference voltage. The LTC3831 uses a synchronous switching architecture with N-channel MOSFETs. Additionally, the chip senses output current through the drain-source resistance of the upper N-channel FET, providing an adjustable current limit without a current sense resistor.

The LTC3831 operates with input supply voltage as low as 3V and with a maximum duty cycle of >91%. It includes a fixed frequency PWM oscillator for low output ripple operation. The 200kHz free-running clock frequency can be externally adjusted or synchronized with an external signal from 100kHz to above 500kHz. In shutdown mode, the LTC3831 supply current drops to <10µA.

Features High Power Switching Regulator Controller for DDR Memory Termination VOUT Tracks 1/2 of VIN or External VREF No Current Sense Resistor Required Low Input Supply Voltage Range: 3V to 8V Maximum Duty Cycle >91% Over Temperature Drives All N-Channel External MOSFETs High Efficiency: Over 95% Possible Programmable Fixed Frequency Operation: 100kHz to 500kHz External Clock Synchronization Operation Programmable Soft-Start Low Shutdown Current: <10µA Overtemperature Protection Available in 16-Pin Narrow SSOP Package Typical Application

Applications DDR SDRAM Termination SSTL_2 Interface SSTL_3 Interface Packaging

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