MAX105:Dual, 6-Bit, 800Msps ADC with On-Chip, Wideband Input Amplifier

The MAX105 is a dual, 6-bit, analog-to-digital converter (ADC) designed to allow fast and precise digitizing of in-phase (I) and quadrature (Q) baseband signals. The MAX105 converts the analog signals of both I and Q components to digital outputs at 800Msps while achieving a signal-to-noise ratio (SNR) of typically 37dB with an input frequency of 200MHz, and an integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.25 LSB. The MAX105 analog input preamplifiers feature a 400MHz, -0.5dB, and a 1.5GHz, -3dB analog input bandwidth. Matching channel-to-channel performance is typically 0.04dB gain, 0.1 LSB offset, and 0.2 degrees phase. Dynamic performance is 36.4dB signal-to-noise plus distortion (SINAD) with a 200MHz analog input signal and a sampling speed of 800MHz. A fully differential comparator design and encoding circuits reduce out-of-sequence errors, and ensure excellent metastable performance of only one error per 1016 clock cycles. In addition, the MAX105 provides LVDS digital outputs with an internal 6:12 demultiplexer that reduces the output data rate to one-half the sample clock rate. Data is output in two's complement format. The MAX105 operates from a +5V analog supply and the LVDS output ports operate at +3.3V. The data converter's typical power dissipation is 2.6W. The device is packaged in an 80-pin, TQFP package with exposed paddle, and is specified for the extended (-40° C to +85°C) temperature range. For a lower-speed, 400Msps version of the MAX105, please refer to the MAX107 data sheet.

Key Features
  • Two Matched 6-Bit, 800Msps ADCs
  • Excellent Dynamic Performance
    • 36.4dB SINAD at fIN ≈ 200MHz and
    • fCLK ≈ 800MHz
  • Typical INL and DNL: ±0.25 LSB
  • Channel-to-Channel Phase Matching: ±0.2°
  • Channel-to-Channel Gain Matching: ±0.04dB
  • 6:12 Demultiplexer reduces the Data Rates to 400MHz
  • Low Error Rate: 1016 Metastable States at 800Msps
  • LVDS Digital Outputs in Two's Complement Format
MAX105: Pin Configuration
MAX105: Pin Configuration
Applications/Uses
  • Communication Systems
  • Test Instrumentation
  • VSAT Receivers
  • Wireless Local Area Networks (WLANs)
DataSheet
titleDownload file
MAX105 Data SheetMAX105.pdf
Parametrics
Part NumberInput Chan.Resolution
(bits)
Sample Rate
(Msps)
AC Specs
(MHz)
SFDR
(dBc)
ENOB
(bits)
SINAD
(dB)
SNR
(dB)
THD
(dB)
DNL
(±LSB)
INL
(±LSB)
Full Pwr. BW
(MHz)
ICC
(mA)
Data Bus InterfacePackage/PinsBudgetary
Price
max ≥@ fINminminmintypSee Notes
MAX10526800200455.836.437-44.50.250.2400650µP/8
Demuxed
LVPECL
TQFP-EP/80$37.97 @1k
Design kits & evaluation modules
Quality and Environmental Data
Related Products
  • MAX107:Dual, 6-Bit, 400Msps ADC with On-Chip, Wideband Input Amplifier
  • MAX108:±5V, 1.5Gsps, 8-Bit, Ultra High-Speed, A to D Converter with On-Chip 2.2GHz Track/Hold Amplifier
  • MAX106:±5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
  • MAX104:±5V, 1Gsps, 8-Bit ADC with On-Chip 2.2GHz Track/Hold Amplifier
  • MAX1002:Low-Power, 60Msps, Dual, 6-Bit ADC
  • MAX1003:Low-Power, 90Msps, Dual 6-Bit ADC
Ordering Information
Part NumberStatusRecommended ReplacementPackageTempRoHS
MAX105ECS+ActiveTQFP-EP,;80 pin;196 mm²-40°C to +85°CLead Free
MAX105ECS+TActiveTQFP;-40°C to +85°CSee data sheet
MAX105ECS-DNo Longer AvailableMAX105ECS+TQFP;80 pin-40°C to +85°CSee data sheet
MAX105ECS-TDNo Longer AvailableMAX105ECS+TQFP;80 pin-40°C to +85°CSee data sheet
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