MAXQ1103：DeepCover Secure Microcontroller with Rapid Zeroization Technology and Cryptography

Cryptographic Microcontroller with Advanced Physical Security and Encrypted External Bus

DeepCover® embedded security solutions cloak sensitive data under multiple layers of advanced physical security to provide the most secure key storage possible. The DeepCover Secure Microcontroller (MAXQ1103) is a low-power, 32-bit RISC device that combines high-performance, single-cycle processing, sophisticated tamper-detection technology, and cryptographic hardware. Advanced security features are designed to meet the stringent requirements of regulations such as ITSEC E3 High, FIPS 140-2 Level 3, and the Common Criteria Certifications. The MAXQ1103 is targeted at electronic commerce, banking, and data security systems that require the highest levels of secure access control, secure data storage, digital signature, or certificate authentication. A secure memory protection unit protects critical internal and external memory against tampering with triple-DES (3DES) encryption. Activation of a tamper sensor causes a rapid zeroization of critical data. An internal physical shield layer increases the complexity and cost of a physical attack against the die. A 32-bit MAXQ30 core powers the cryptographically secure MAXQ1103. Applications are supported with 512KB of high-performance internal flash memory for code/data storage and 32KB SRAM. Up to 8MB of additional external program and data memory is supported through a dedicated word-wide memory bus with programmable wait states. Additional peripherals such as serial I/O, 16-bit timers, hardware math accelerator, ISO 7816 UART, and a USB controller increase system utility while reducing component count. System security is enhanced by the addition of high-speed cryptographic hardware accelerators for ECDSA, DSA, RSA, Secure Hash Algorithm, and triple-key 3DES. The embedded hash engine supports multiple hash functions recommended by the National Institute of Standards and Technology (NIST). The true hardware random-number generator (RNG) supports FIPS 186-2 with an available software library. Note: Designers must have following documents to fully use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical specifications. Errata sheets contain deviations from published specifications. The user's guides offer detailed information about device features and operation. MAXQ1103 IC data sheet MAXQ1103 revision-specific errata sheet (Click here for availability) MAXQ® Family User's Guide MAXQ Family User's Guide: MAXQ1103 Supplement

Key Features

High-Performance 32-Bit MAXQ30 RISC Core
DC to 25MHz Operation, Approaching 1MIPS per MHz
Dual 1.8V Core/3.3V I/O Enables Low Power/Flexible Interfacing
5V Tolerant I/O
Up to 32 General-Purpose I/O Pins
34 Instructions, Most Single Cycle
Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement
Virtually Unlimited Software Stack
16-Bit Instruction Word, 32-Bit Internal Data Bus
16 x 32-Bit Accumulators
Security Features
- 3DES-Encrypted External Memory Bus Prevents Eavesdropping
- Tamper Sensors Rapidly "Zeroize" Internal Keys and User Data When:
  - Out-of-Range Temperature/Voltage Detected
  - User-Defined Self-Destruct Inputs (SDIx) Activated
- Internal Cryptographic Hardware Includes:
  - DES Engine Supporting Single DES and 2/3-Key 3DES Operations
  - Public-Key Cryptographic Accelerator for ECDSA (160-, 192-, and 256-Key Strength)
  - Public-Key Cryptographic Accelerator for DSA and RSA (1024- and 2048-Key Strength)
  - Hardware Hash Engine Supports SHA-1, SHA-224, SHA-256
- Unresettable True-Time Clock Self-Imposes Expiration Dates and Date/Timestamping
Memory Features
- Secure Memory Management Unit and 4KB Instruction Cache
- 512KB of Internal Flash Program Memory
- 3KB Internal Program Memory SRAM
- 32KB Internal Data SRAM, Including 1KB Battery-Backed NV SRAM
- Linear Address Space Directly Accesses Up to 8MB of External Program/Data Memory
Peripheral Features
- USB Device Controller with Four Endpoint Buffers
- ISO 7816 UART with FIFO with Two Physically Separate Communication Buses
Power Management Features
In-System Programming Through Debug Port or Serial Port
Ultra-Low Battery Leakage to Support NV RAM and Security Sensors (150nA)

Applications/Uses

ATM Keyboards
Certificate Authentication
Electronic Commerce
Electronic Signature Generator
EMV® Banking
Pay-per-Play
PCI Terminals
PIN Pads
Secure Access Control
Secure Data Storage

DataSheet

title	Download file
MAXQ1103 Data Sheet	MAXQ1103.pdf
Errata MAXQ1103	MAXQ1103B1.pdf
Errata MAXQ1103	MAXQ1103B2.pdf
Errata MAXQ1103	MAXQ1103B3.pdf

Parametrics

Part Number	MCU Core	Core Clock Speed (MHz)	Data Processing	Internal Flash (KBytes)	Internal SRAM (KBytes)	USARTs	USB	GPIO Pins	Timer Features	Package/Pins
Part Number	MCU Core	max	Data Processing	Internal Flash (KBytes)	Internal SRAM (KBytes)	USARTs	USB	max	Timer Features	Package/Pins
MAXQ1103	MAXQ30 (RISC)	25	32-bit	512	32	2	USB Device Port	32	RTC Watchdog	TQFP/144