Features

• Optimized for high performance applications
• Efficient architecture with low CPU overhead
• Easily interfaces to most 16-bit embedded CPU's
• 1.8V to 3.3V variable voltage I/O accommodates wide range of I/O signaling without voltage level shifters
• Integrated PHY with HP Auto-MDIX support
• Integrated checksum offload engine helps reduce CPU load
• Low pin count and small body size package for small form factor system designs
• Cable, satellite, and IP set-top boxes
• Digital video recorders and DVD recorder/players
• Digital TV
• Digital media clients/servers and home gateways
• Video-over IP solutions, IP PBX & video phones
• Wireless routers & access points
• High-end audio distribution systems
• Non-PCI Ethernet controller for high performance applications 16-bit interface with fast bus cycle times Burst-mode read support
• 16-bit interface with fast bus cycle times
• Burst-mode read support
• Minimizes dropped packets Internal buffer memory can store over 200 packets Automatic PAUSE and back-pressure flow control
• Internal buffer memory can store over 200 packets
• Automatic PAUSE and back-pressure flow control
• Minimizes CPU overhead Supports Slave-DMA Interrupt Pin with Programmable Hold-off timer
• Supports Slave-DMA
• Interrupt Pin with Programmable Hold-off timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most Embedded CPU's or SoC's
• Reduced-Power Modes Numerous power management modes Wake on LAN Magic packet wakeup Wakeup indicator event signal Link Status Change
• Numerous power management modes
• Wake on LAN
• Magic packet wakeup
• Wakeup indicator event signal
• Link Status Change
• Single chip Ethernet controller Fully compliant with IEEE 802.3/802.3u standards Integrated Ethernet MAC and PHY 10BASE-T and 100BASE-TX support Full- and Half-duplex support Full-duplex flow control Backpressure for half-duplex flow control Preamble generation and removal Automatic 32-bit CRC generation and checking Automatic payload padding and pad removal Loop-back modes
• Fully compliant with IEEE 802.3/802.3u standards
• Integrated Ethernet MAC and PHY
• 10BASE-T and 100BASE-TX support
• Full- and Half-duplex support
• Full-duplex flow control
• Backpressure for half-duplex flow control
• Preamble generation and removal
• Automatic 32-bit CRC generation and checking
• Automatic payload padding and pad removal
• Loop-back modes
• Flexible address filtering modes One 48-bit perfect address 64 hash-filtered multicast addresses Pass all multicast Promiscuous mode Inverse filtering Pass all incoming with status report Disable reception of broadcast packets
• One 48-bit perfect address
• 64 hash-filtered multicast addresses
• Pass all multicast
• Promiscuous mode
• Inverse filtering
• Pass all incoming with status report
• Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY Supports HP Auto-MDIX Auto-negotiation Supports energy-detect power down
• Supports HP Auto-MDIX
• Auto-negotiation
• Supports energy-detect power down
• Host bus interface Simple, SRAM-like interface 16-bit data bus 16Kbyte FIFO with flexible TX/RX allocation One configurable host interrupt
• Simple, SRAM-like interface
• 16-bit data bus
• 16Kbyte FIFO with flexible TX/RX allocation
• One configurable host interrupt
• Miscellaneous features Small form factor, 56-pin QFN RoHS Compliant package Integrated 1.8V regulator Integrated checksum offload engine Mixed endian support General Purpose Timer Optional EEPROM interface Support for 3 status LEDs multiplexed with Programmable GPIO signals
• Small form factor, 56-pin QFN RoHS Compliant package
• Integrated 1.8V regulator
• Integrated checksum offload engine
• Mixed endian support
• General Purpose Timer
• Optional EEPROM interface
• Support for 3 status LEDs multiplexed with Programmable GPIO signals
• Single 3.3V Power Supply with Variable Voltage I/O
• Commercial and Industrial Temperature Support

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