Features

• AES Engine with 128,192 or 256-Bit Key
• Supports ECB, CBC, OFB, CTR and CFB128 modes
• DES/Triple DES (TDES) Engine: Supports 2-Key and 3-Key EDE or DED TDES
• Supports up to Three Unique Keys for TDES
• Programmatically Secure
• True Random Number Generator
• Pseudorandom Number Generator
• Non-Readable, On-Chip, OTP Key Storages
• Extreme Low-Power Current Consumption for Deep Sleep: WDT: 270 nA @ 3.3V typical RTCC: 400 nA @ 32 kHz, 3.3V typical Deep Sleep current, 40 nA, 3.3V typical
• WDT: 270 nA @ 3.3V typical
• RTCC: 400 nA @ 32 kHz, 3.3V typical
• Deep Sleep current, 40 nA, 3.3V typical
• Multiple Power Management Options for Extreme Power Reduction VBAT, Deep Sleep, Sleep and Idle Mode, Doze Mode.
• VBAT, Deep Sleep, Sleep and Idle Mode, Doze Mode.
• Alternate Clock modes allow On-the-Fly Switching to a Lower Clock Speed for Selective Power Reduction
• USB v2.0 On-The-Go (OTG) Compliant
• Dual Role Capable; can Act as Either Host or Peripheral
• Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode
• Full-Speed USB Operation in Device mode
• High-Precision PLL for USB
• USB Device mode Operation from FRC Oscillator: No crystal oscillator required
• No crystal oscillator required
• Supply Voltage Range of 2.0V to 3.6V
• Up to 16 MIPS Operation @ 32 MHz
• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16 x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture (ISA)
• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory
• 10/12-Bit, 12-Channel Analog-to-Digital (A/D) Converter: Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit) Conversion available during Sleep and Idle
• Conversion rate of 500 ksps (10-bit), 200 ksps (12-bit)
• Conversion available during Sleep and Idle
• Three Rail-to-Rail, Enhanced Analog Comparators with Programmable Input/Output Configuration
• Three On-Chip Programmable Voltage References
• Charge Time Measurement Unit (CTMU): Used for capacitive touch sensing, up to 12 channel Time measurement down to 100 ps resolution Operation in Sleep mode
• Used for capacitive touch sensing, up to 12 channel
• Time measurement down to 100 ps resolution
• Operation in Sleep mode
• Peripheral Pin Select (PPS); Allows Independent I/O Mapping of many Peripherals
• Five 16-Bit Timers/Counters with Prescaler
• Six-Channel DMA supports All Peripheral modules
• Six Input Capture modules, each with a Dedicated 16-Bit Timer
• Six Output Compare/PWM modules, each with a Dedicated 16-Bit Timer
• Hardware Real-Time Clock/Calendar (RTCC)
• Three 3-Wire/4-Wire SPI modules Support four Frame modes Variable FIFO buffer I2S mode Variable width from 2-bit to 32-bit
• Support four Frame modes
• Variable FIFO buffer
• I2S mode
• Variable width from 2-bit to 32-bit
• Two I2C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing
• Programmable 32-Bit Cyclic Redundancy Check (CRC) Generator
• Four UART modules Support RS-485, RS-232 and LIN/J2602 On-chip hardware encoder/decoder for IrDA® Smart Card ISO 7816 support on UART1 and UART2 only: T = 0 protocol with automatic error handling T = 1 protocol Dedicated Guard Time Counter (GTC) Dedicated Waiting Time Counter (WTC) Auto-wake-up on Auto-Baud Detect (ABD) 4-level deep FIFO buffer
• Support RS-485, RS-232 and LIN/J2602
• On-chip hardware encoder/decoder for IrDA®
• Smart Card ISO 7816 support on UART1 and UART2 only: T = 0 protocol with automatic error handling T = 1 protocol Dedicated Guard Time Counter (GTC) Dedicated Waiting Time Counter (WTC)
• T = 0 protocol with automatic error handling
• T = 1 protocol
• Dedicated Guard Time Counter (GTC)
• Dedicated Waiting Time Counter (WTC)
• Auto-wake-up on Auto-Baud Detect (ABD)
• 4-level deep FIFO buffer

Parameter