The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.
Name/Description | Modified Date |
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2.5 V/3.3 V 16-bit D-type transparent latch; 3-state (REV 6.0) PDF (123.0 kB) 74ALVCH16373 [English] | 10 Jul 2012 |
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Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Name/Description | Modified Date |
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電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Name/Description | Modified Date |
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ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
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plastic thin shrink small outline package; 48 leads; body width 6.1 mm (REV 1.0) PDF (467.0 kB) SOT362-1 [English] | 08 Feb 2016 |
Name/Description | Modified Date |
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TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 5.0) PDF (242.0 kB) SOT362-1_118 [English] | 15 Apr 2013 |
Name/Description | Modified Date |
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Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Output drive capability (mA) | Package version | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74ALVCH16373DGG | Active | ALVC | 2.3 - 3.6 | Latches/registered drivers | 16-bit D-type transparent latch with bus hold (3-state) | LVTTL | +/- 24 | SOT362-1 | 2.1 | 16 | low | -40~85 | 82 | 1.8 | 35 | TSSOP48 | 48 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74ALVCH16373DGG | SOT362-1 | SSOP-TSSOP-VSO-WAVE | Bulk Pack | Active | 74ALVCH16373DGG,11 (9352 051 20112) | ALVCH16373 | 74ALVCH16373DGG | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||
Reel 13" Q1/T1 | Active | 74ALVCH16373DGG:11 (9352 051 20118) | ALVCH16373 | 74ALVCH16373DGG | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | |||||
Tube in Drypack | Withdrawn | 74ALVCH16373DGG,51 (9352 051 20512) | ALVCH16373 | 74ALVCH16373DGG | week 14, 2005 | 123.8 | 3.87 | 2.58E8 | 2 | 2 |