74ALVCH16952DGG: 16-bit registered transceiver (3-State)

The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs.

74ALVCH16952DGG: Product Block Diagram

Outline 3d SOT364-1

Data Sheets (1)

Name/Description	Modified Date
16-bit registered transceiver (3-State) (REV 2.0) PDF (92.0 kB) 74ALVCH16952 [English]	15 Feb 2010

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]	15 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvch16952 IBIS model (REV 1.0) ibs ALVCH16952 4/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Package version	Output drive capability	t_pd (ns)	No of bits	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVCH16952DGG	Active	ALVC	1.65 - 3.6	Transceivers	TTL	16-bit registered transceiver with bus hold (3-state)	SOT364-1	+/- 24	3.2	16	150	low		93	21.0		TSSOP56	56

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVCH16952DGG		SOT364-1	SSOP-TSSOP-VSO-WAVE	Tube in Drypack	Active	74ALVCH16952DGGS (9352 628 01512)	ALVCH16952	74ALVCH16952DGG		Always Pb-free	123.8	3.87	2.58E8	2	2
74ALVCH16952DGG		SOT364-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1 in Drypack	Active	74ALVCH16952DGGY (9352 628 01518)	ALVCH16952	74ALVCH16952DGG		Always Pb-free	123.8	3.87	2.58E8	2	2