74ALVT16823DL: 18-bit bus-interface D-type flip-flop with reset and enable; 3-state

The 74ALVT16823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

The 74ALVT16823 has two 9-bit wide buffered registers with clock enable (pin nCE) and master reset (pin nMR) which are ideal for parity bus interfacing in high microprogrammed systems.

The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop.

It is designed for VCC operation from 2.5 V to 3.0 V with I/O compatibility to 5 V.

74ALVT16823DL: Product Block Diagram

74ALVT16823DL: Block Diagram

Outline 3d SOT371-1

Data Sheets (1)

Name/Description	Modified Date
18-bit bus-interface D-type flip-flop with reset and enable; 3-state (REV 4.0) PDF (115.0 kB) 74ALVT16823 [English]	02 Aug 2005

Application Notes (8)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]	02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]	01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]	01 Jan 1998
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (2)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 56 leads; body width 7.5 mm (REV 1.0) PDF (530.0 kB) SOT371-1 [English]	08 Feb 2016

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvt16823 IBIS model (REV 1.0) ibs ALVT16823 4/7/2013

SPICE model

alvt16 Spice model (REV 1.0) ZIP ALVT16 5/7/2013

Ordering Information

Product	Status	Family	Function	V_CC (V)	Description	Logic switching levels	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVT16823DL	Active	ALVT	D-type flip-flops	2.3 - 3.6	positive-edge trigger (3-state)	TTL	SOT371-1	-32/+64	1.9	250	medium	-40~85	84	24.0		SSOP56	56

Package Information

Product ID	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVT16823DL	SOT371-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Tube in Drypack	Active	74ALVT16823DL,512 (9352 610 20512)	ALVT16823	74ALVT16823DL	week 13, 2005	70.8	1.33	7.52E8	1	2
			Reel 13" Q1/T1 in Drypack	Active	74ALVT16823DL,518 (9352 610 20518)	ALVT16823	74ALVT16823DL	week 13, 2005	70.8	1.33	7.52E8	1	2
			Reel 13" Q1/T1	Withdrawn	74ALVT16823DL,118 (9352 610 20118)	ALVT16823	74ALVT16823DL		70.8	1.33	7.52E8	1	NA