74AUP1G79GV: Low-power D-type flip-flop; positive-edge trigger

The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

74AUP1G79GV: Product Block Diagram
74AUP1G79GV: Block Diagram
74AUP1G79GV: Block Diagram
Outline 3d SOT753
Data Sheets (1)
Name/DescriptionModified Date
Low-power D-type flip-flop; positive-edge trigger (REV 6.0) PDF (369.0 kB) 74AUP1G79 [English]28 Jun 2012
Application Notes (3)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Pin FMEA for AUP family (REV 1.0) PDF (53.0 kB) AN11052 [English]06 May 2011
PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English]30 Oct 2002
Brochures (3)
Name/DescriptionModified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]16 Feb 2015
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic (REV 1.0) PDF (1.4 MB) 75017458 [English]13 Oct 2014
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]20 May 2014
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic surface-mounted package; 5 leads (REV 1.0) PDF (243.0 kB) SOT753 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (186.0 kB) SOT753_125 [English]29 Nov 2012
Supporting Information (1)
Name/DescriptionModified Date
MAR_SOT753 Topmark (REV 1.0) PDF (89.0 kB) MAR_SOT753 [English]03 Jun 2013
IBIS Model
Ordering Information
ProductStatusFamilyVCC (V)FunctionLogic switching levelsDescriptionPackage versionOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74AUP1G79GVActiveAUP1.1 - 3.6D-type flip-flopsCMOSpositive-edge triggerSOT753+/- 1.99.1400ultra low-40~12526862.1167TSOP55
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateMSLMSL LF
74AUP1G79GVSOT753Reel 7" Q3/T4, ReverseActive74AUP1G79GV,125 (9352 900 77125)p7974AUP1G79GVAlways Pb-free11
Low-power D-type flip-flop; positive-edge trigger 74AUP1G79GX
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Pin FMEA for AUP family 74AUP1T34GW-Q100
PicoGate Logic footprints NX3L4684
電圧レベルシフタ 74AVC16245DGG-Q100
NXP® ultra-low-power CMOS logic 74AUP1G/2G/3Gxxx: Advanced, ultra-low-power CMOS logic 74AUP1G86GW-Q100
Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
MAR_SOT753 Topmark 74LVC1G17_Q100
74AUP1G79 IBIS model 74AUP1G79GX
plastic surface-mounted package; 5 leads 74LVC1G17_Q100
Tape reel SMD; reversed product orientation 12NC ending 125 74LVC1G17_Q100
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