74LVC161PW: Presettable synchronous 4-bit binary counter; asynchronous reset

The 74LVC161 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pins CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level regardless of the levels at input pins CP, PE, CET and CEP (thus providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula: fmax = 1/ (tPHL(max)+tsu)

It is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families.

74LVC161PW: Product Block Diagram
Outline 3d SOT403-1
Data Sheets (1)
Name/DescriptionModified Date
Presettable synchronous 4-bit binary counter; asynchronous reset (REV 6.0) PDF (156.0 kB) 74LVC161 [English]30 Sep 2013
Application Notes (5)
Name/DescriptionModified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]15 Sep 1995
Selector Guides (2)
Name/DescriptionModified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
Package Information (1)
Name/DescriptionModified Date
plastic thin shrink small outline package; 16 leads; body width 4.4 mm (REV 1.0) PDF (300.0 kB) SOT403-1 [English]08 Feb 2016
Packing (1)
Name/DescriptionModified Date
TSSOP16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (218.0 kB) SOT403-1_118 [English]08 Apr 2013
Supporting Information (1)
Name/DescriptionModified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]08 Oct 2009
IBIS Model
SPICE model
Ordering Information
ProductStatusFamilyFunctionVCC (V)DescriptionOutput drive capability (mA)Package versionLogic switching levelstpd (ns)Power dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVC161PWActiveLVCBinary counters/timers1.2 - 3.6asynchronous reset+/- 24SOT403-1CMOS/LVTTL4.9low-40~1251254.654.7TSSOP1616
Package Information
Product IDPackage DescriptionOutline VersionReflow/Wave SolderingPackingProduct StatusPart NumberOrdering code(12NC)MarkingChemical ContentRoHS / Pb Free / RHFLeadFree Conversion DateEFRIFR(FIT)MTBF(hour)MSLMSL LF
74LVC161PWSOT403-1SSOP-TSSOP-VSO-WAVEReel 13" Q1/T1Active74LVC161PW,118 (9352 105 30118)LVC16174LVC161PWweek 10, 2005123.83.872.58E811
Bulk PackActive74LVC161PW,112 (9352 105 30112)LVC16174LVC161PWweek 10, 2005123.83.872.58E811
Presettable synchronous 4-bit binary counter; asynchronous reset 74LVC161PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
Pin FMEA for LVC family 74LVC1G123_Q100
Power considerations when using CMOS and BiCMOS logic devices 74AHCT244PW
Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvc161 IBIS model 74LVC161PW
lvc Spice model 74LVC3G17GT
SOT403-1 LPC812M101JDH16
SSOP-TSSOP-VSO-WAVE LPC1114FDH28
Reel 13" Q1/T1 LPC812M101JDH16
74LVC161
PCA9633