74LVC16374ADL: 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state outputs for bus oriented applications. It consists of two sections of eight positive edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for each octal.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

74LVC16374ADL: Product Block Diagram

Outline 3d SOT370-1

Data Sheets (1)

Name/Description	Modified Date
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state (REV 11.0) PDF (138.0 kB) 74LVC_LVCH16374A [English]	16 Jan 2013

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English]	04 Feb 2011
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English]	05 Feb 2002
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English]	19 Apr 2013

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

lvc163 IBIS model (REV 1.0) ibs LVC163 4/7/2013
lvc16374a IBIS model (REV 1.0) ibs LVC16374A 4/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Description	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74LVC16374ADL	Active	LVC	1.2 - 3.6	D-type flip-flops	CMOS/LVTTL	positive-edge trigger (3-state)	SOT370-1	+/- 24	3.8	150	low	-40~125	88	25.0		SSOP48	48

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74LVC16374ADL		SOT370-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74LVC16374ADL,118 (9352 351 80118)	LVC16374A	74LVC16374ADL		week 13, 2005	123.8	3.87	2.58E8	1	1
74LVC16374ADL		SOT370-1		Bulk Pack	Active	74LVC16374ADL,112 (9352 351 80112)	LVC16374A	74LVC16374ADL		week 13, 2005	123.8	3.87	2.58E8	1	1