The 74LVC163 is a synchronous presettable binary counter which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (pin CP). The outputs (pins Q0 to Q3) of the counters may be preset to a HIGH-level or LOW-level. A LOW-level at the parallel enable input (pin PE) disables the counting action and causes the data at the data inputs (pins D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable inputs (pin CEP and CET). A LOW-level at the master reset input (pin MR) sets all four outputs of the flip-flops (pins Q0 to Q3) to LOW-level after the next positive-going transition on the clock input (pin CP) (provided that the set-up and hold time requirements for PE are met). This action occurs regardless of the levels at input pins PE, CET and CEP. This synchronous reset feature enables the designer to modify the maximum count with only one external NAND gate.
The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (pin CEP and CET) must be HIGH in count. The CET input is fed forward to enable the terminal count output (pin TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH-level output of Q0. This pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters is determined by tPHL (propagation delay CP to TC) and tsu (set-up time CEP to CP) according to the formula: fmax=1/(tPHL(max)+tsu)
Name/Description | Modified Date |
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Presettable synchronous 4-bit binary counter; synchronous reset (REV 6.0) PDF (155.0 kB) 74LVC163 [English] | 20 Nov 2012 |
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Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
Pin FMEA for LVC family (REV 1.0) PDF (44.0 kB) AN11009 [English] | 04 Feb 2011 |
Power considerations when using CMOS and BiCMOS logic devices (REV 1.0) PDF (100.0 kB) AN263 [English] | 05 Feb 2002 |
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
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ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
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plastic thin shrink small outline package; 16 leads; body width 4.4 mm (REV 1.0) PDF (300.0 kB) SOT403-1 [English] | 08 Feb 2016 |
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TSSOP16; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (218.0 kB) SOT403-1_118 [English] | 08 Apr 2013 |
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Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
Product | Status | Family | Function | VCC (V) | Output drive capability (mA) | Description | Package version | Logic switching levels | tpd (ns) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74LVC163PW | Active | LVC | Binary counters/timers | 1.2 - 3.6 | +/- 24 | synchronous reset | SOT403-1 | CMOS/LVTTL | 4.9 | low | -40~125 | 125 | 4.6 | 54.7 | TSSOP16 | 16 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
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74LVC163PW | ![]() | SOT403-1 | SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74LVC163PW,118 (9352 105 60118) | LVC163 | 74LVC163PW | ![]() ![]() ![]() | week 10, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
Bulk Pack | Active | 74LVC163PW,112 (9352 105 60112) | LVC163 | 74LVC163PW | ![]() ![]() ![]() | week 10, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |