MAC57D5xx: Ultra-Reliable Multi-Core ARM®-based MCU for Clusters and Display Management

The MAC57D5xx MCU family is a multi-core architecture solution for mid-range instrument cluster and industrial applications. This MCU is based on the ARM® Cortex®-M processor for real time and an ARM® Cortex®-A processors for applications and human machine interfaces that offer leading edge performance & scalability.

The MAC57D5xx MCU supports up to 2 WVGA resolution displays, one with in line head-up display hardware warping. The graphics content is generated using a powerful Vivante 2D GPU and the 2D animation and composition engine, to reduce memory footprint for content creation, integrated stepper motor drivers and a powerful I/O processor.

The MAC57D5xx MCU integrates NXP®.rsquo;s latest SHE-compliant CSE2 engine and delivers support ISO26262 ASIL-B functional safety compliance.

MAC57D5XX Block Diagram

MAC57D5x Instrument Cluster with HUD

特性

ARM®-based multi-core architecture platform
- ARM® Cortex®-A5, 32-bit CPU (application processor)
- ARM® Cortex®-M4, 32-bit CPU (vehicle processor)
- ARM® Cortex®-M0+, 32-bit CPU (I/O processor)
ARM® Cortex®-A5, 32-bit CPU (application processor)
ARM® Cortex®-M4, 32-bit CPU (vehicle processor)
ARM® Cortex®-M0+, 32-bit CPU (I/O processor)
Intelligent stepper motor drive with stepper stall detect
Low-power mode peripheral management
Supports 2 x WVGA displays
On-the-fly Head Up Display (HUD) warping engine
Functional safety & security compliant
Ethernet 10/100 + AVB (ENET)
Autonomous real time clock (self calibrating)
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature
Ultra-Reliable MCUs

Name/Description	Type	Modified Date
MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFS	Fact Sheets	08 Aug 2016
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWP	White Papers	18 Mar 2015

Data Sheets (1)

Name/Description	Modified Date
SAC57D54H Data Sheet (REV 5) PDF (1.3 MB) SAC57D54H	17 May 2016

Application Notes (3)

Name/Description	Modified Date
AN5285: MAC57D5xx Start-Up Sequence - Application notes (REV 0) PDF (324.5 kB) AN5285	02 May 2016
AN5265, MAC57D5xx Hardware Design Guidelines - Application note (REV 0) PDF (1.0 MB) AN5265	28 Apr 2016
AN5072, Introduction to Embedded Graphics with NXP® Devices-Application Notes (REV 0) PDF (796.7 kB) AN5072	09 Feb 2015

Reference Manuals (1)

Name/Description	Modified Date
SAC57D54H Reference Manual (REV 4.2) PDF (19.9 MB) SAC57D54HRM	18 May 2016

Users Guides (1)

Name/Description	Modified Date
MAC57D5xxUG, MAC57D5xx Customer Evaluation Boards (REV 0) PDF (1.4 MB) MAC57D5XXUG	04 May 2016

Engineering Bulletins (1)

Name/Description	Modified Date
EB833: MAC57D5xx STCU BIST Configuration (REV 0) PDF (295.6 kB) EB833	20 Mar 2016

Fact Sheets (1)

Name/Description	Modified Date
MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFS	08 Aug 2016

White Papers (1)

Name/Description	Modified Date
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWP	18 Mar 2015

Ordering Information

Product	Status	Package Type and Termination Count	Core Type	Operating Frequency (Max) (MHz)	L1 Cache	Internal RAM (KB)	Internal Flash (KB)	CAN	I2C	SPI	LinFlex D	Memory / Peripheral Protection	eDMA	External Memory Supported	Video/Display features	Timer/PWM
SAC57D54HCVMO	Active	MAPBGA 516	ARM Cortex-M4, ARM Cortex-M0+ IOP, ARM Cortex-A5	320	32/32 on A5	1300	4000	3	2	5	3	Yes	2x 16ch	32-Bit DDR2 DRAM (320mhz), 16-Bit SDR DRAM (160mhz), 2x Dual DDR QuadSPI	2x 2D-ACE, HUD Warping Engine, Video Input Unit, Segment LCD, OpenVG 1.1	8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D53MCVLT	Active	LQFP 208	ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4	320	32/32 on A5	1300	3000	3	2	5	3	Yes	2x 16ch	2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)	OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit	8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D54HCVLT	Active	LQFP 208	ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4	320	32/32 on A5	1300	4000	3	2	5	3	Yes	2x 16ch	2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)	OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit	8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D53MCVMO	Active	MAPBGA 516	ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4	320	32/32 on A5	1300	3000	3	2	5	3	Yes	2x 16ch	2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)	OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit	8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer
SAC57D52LCVLT	Active	LQFP 208	ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4	320	32/32 on A5	1300	2000	3	2	5	3	Yes	2x 16ch	2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz)	OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit	8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer

Package Information

Package Description	Outline Version	Packing	Product Status	Part Number	Chemical Content	MSL	PPT (°C)
MAPBGA 516 27SQ*2.0 P1.0	98ASA00623D	MPQ - 200 BRICKPOQ - 400 BOX	Active	SAC57D54HCVMO	SAC57D54HCVMO.pdf	3	260
MAPBGA 516 27SQ*2.0 P1.0	98ASA00623D	MPQ - 200 BRICKPOQ - 400 BOX	Active	SAC57D53MCVMO	SAC57D53MCVMO.pdf	3	260
LQFPEP 208 28SQ P0.5	98ASA00649D	MPQ - 180 BRICKPOQ - 360 BOX	Active	SAC57D54HCVLT	SAC57D54HCVLT.pdf	3	260
		MPQ - 180 BRICKPOQ - 360 BOX	Active	SAC57D53MCVLT	SAC57D53MCVLT.pdf	3	260
		MPQ - 180 BRICKPOQ - 360 BOX	Active	SAC57D52LCVLT	SAC57D52LCVLT.pdf	3	260