NB3W800L: 3.3 V 100/133 MHz Differential 1:8 HCSL Compatible Push-Pull Clock ZDB/Fanout Buffer for PCIe

The NB3W800L is a low−power 8−output differential buffer that meets all the performance requirements of the DB800ZL specification. The NB3W800L is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. A fixed, internal feedback path maintains low drift for critical QPI applications.

Features
  • 8 Differential Clock Output Pairs @ 0.7 V
  • Low−power NMOS Push−pull HCSL Compatible Outputs
  • Output−to−output Skew <50 ps
  • Input−to−output Delay Variation <100 ps
  • PCIe Gen3 Phase Jitter <1.0 ps RMS
  • QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS
  • Individual OE Control; Hardware Control of Each Output
  • PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
  • 100 MHz or 133 MHz PLL Mode Operation; Supports PCIe and QPI Applications
  • Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream PLL’s
  • Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
  • SMBus Programmable Configurations
Applications
  • Industrial
  • Networking
  • Computing
  • Consumer
End Products
  • Desktop
  • Notebook
  • Switches / Routers
  • Servers
  • Automated Test Equipment
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
NB3W800LNB3W800L (66kB)0May, 2015
Package Drawings (1)
Document TitleDocument ID/SizeRevision
QFN48 6.0x6.0, 0.4P485DP (33.4kB)O
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
Differential 1:8 Push-Pull Clock ZDB/Fanout Buffer for PCIe, 3.3 V, 100/133 MHzNB3W800L/D (146kB)2Jul, 2016
Evaluation Board Documents (5)
Document TitleDocument ID/SizeRevisionRevision Date
NB3W800LMNGEVB Bill Of Materials (ROHS Compliant)NB3W800LMNGEVB_BOM_ROHS.pdf (40kB)0
NB3W800LMNGEVB GUI Evaluation Board User's ManualEVBUM2330/D (438kB)0Nov, 2015
NB3W800LMNGEVB SchematicNB3W800LMNGEVB_SCHEMATIC.pdf (356kB)0
NB3W800LMNGEVB Test ProcedureNB3W800LMNGEVB_TEST_PROCEDURE.pdf (671kB)0
NB3W800LMNGEVB User's ManualNB3W800LMNGEVB_USERS_MANUAL.pdf (1062kB)0
Evaluation/Development Tool Information
ProductStatusComplianceShort Description
NB3W800LMNGEVBActivePb-free3.3 V 100/133 MHz Differential 1:8 HCSLCompatible Push-Pull Clock ZDB/Fanout Buffer for PCIe Evaluation Board
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
NB3W800LMNGActivePb-free Halide freeQFN-48485DP3Tray JEDEC490Contact BDTIC
NB3W800LMNTWGActivePb-free Halide freeQFN-48485DP3Tape and Reel2500Contact BDTIC
NB3W800LMNTXGActivePb-free Halide freeQFN-48485DP3Tape and Reel2500Contact BDTIC
Specifications
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB3W800LMNGBuffer11:8HCSLHCSL3.350087.5100 133.33
NB3W800LMNTWGBuffer11:8HCSLHCSL3.350087.5133.33 100
NB3W800LMNTXGBuffer11:8HCSLHCSL3.350087.5100 133.33
Differential 1:8 Push-Pull Clock ZDB/Fanout Buffer for PCIe, 3.3 V, 100/133 MHz (146kB) NB3W800L
NB3W800L NB3W800L
NB3W800LMNGEVB BOM ROHS NB3W800LMNGEVB
EVBUM2330/D - 438 KB NB3W800LMNGEVB
NB3W800LMNGEVB SCHEMATIC NB3W800LMNGEVB
NB3W800LMNGEVB TEST PROCEDURE NB3W800LMNGEVB
NB3W800LMNGEVB USERS MANUAL NB3W800LMNGEVB
QFN48 6.0x6.0, 0.4P NB3W800L