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SPC564L60L3：32-bit Power Architecture MCU for Automotive Chassis and Safety Applications

The Leopard series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system.

The SPC56XL60/54 family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the SPC56XL60/54 automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users’ implementations.

Key Features

• High-performance e200z4d dual core
• 32-bit Power Architecture® technology CPU
• Core frequency as high as 120 MHz
• Dual issue five-stage pipeline core
• Variable Length Encoding (VLE)
• Memory Management Unit (MMU)
• 4 KB instruction cache with error detection code
• Signal processing engine (SPE)
• Memory available
  • 1 MB flash memory with ECC
  • 128 KB on-chip SRAM with ECC
  • Built-in RWW capabilities for EEPROM emulation
• SIL3/ASILD innovative safety concept: LockStep mode and Fail-safe protection
  • Sphere of replication (SoR) for key components (such as CPU core, eDMA, crossbar switch)
  • Fault collection and control unit (FCCU)
  • Redundancy control and checker unit (RCCU) on outputs of the SoR connected to FCCU
  • Boot-time Built-In Self-Test for Memory (MBIST) and Logic (LBIST) triggered by hardware
  • Boot-time Built-In Self-Test for ADC and flash memory triggered by software
  • Replicated safety enhanced watchdog
  • Replicated junction temperature sensor
  • Non-maskable interrupt (NMI)
  • 16-region memory protection unit (MPU)
  • Clock monitoring units (CMU)
  • Power management unit (PMU)
  • Cyclic redundancy check (CRC) unit
• Decoupled Parallel mode for high-performance use of replicated cores
• Nexus Class 3+ interface
• Interrupts
  • Replicated 16-priority controller
  • Replicated 16-channel eDMA controller
• GPIOs individually programmable as input, output or special function
• Three 6-channel general-purpose eTimer units
• 2 FlexPWM units
  • Four 16-bit channels per module
• Communications interfaces
  • 2 LINFlexD channels
  • 3 DSPI channels with automatic chip select generation
  • 2 FlexCAN interfaces (2.0B Active) with 32 message objects
  • FlexRay module (V2.1 Rev. A) with 2 channels, 64 message buffers and data rates up to 10 Mbit/s
• Two 12-bit analog-to-digital converters (ADCs)
  • 16 input channels
  • Programmable cross triggering unit (CTU) to synchronize ADCs conversion with timer and PWM
• Sine wave generator (D/A with low pass filter)
• On-chip CAN/UART bootstrap loader
• Single 3.0 V to 3.6 V voltage supply
• Ambient temperature range –40 °C to 125 °C
• Junction temperature range –40 °C to 150 °C

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