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SPC56EC64B3：32-bit Power Architecture MCU for Automotive Body and Gateway Applications

The 32-bit SPC564Bxx and SPC56ECxx automotive microcontrollers are a family of System-on-Chip (SoC) devices designed to be central to the development of the next wave of central vehicle body controller, high end gateway, smart junction box, front module and combined body controller and gateway applications.

The SPC564Bxx and SPC56ECxx family is one of a series of next-generation automotive microcontrollers based on the Power Architecture‚ architecture and designed specifically for embedded automotive applications. This document describes the features of the SPC564Bxx and SPC56ECxx family and highlights important electrical and physical characteristics of the devices.

The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and are supported with software drivers, operating systems and configuration code to assist with user implementations.

Key Features

• e200z4d, 32-bit Power Architecture®
  • up to 120MHz and 200MIPs operation
• e200z0h, 32-bit Power Architecture
  • up to 80MHz and 75MIPs operation
• Memory
  • Up to 3MByte on-chip Flash with ECC
  • Up to 256KByte on-chip SRAM with ECC
  • 64KByte on-chip Data Flash with ECC
  • 16-entry memory protection unit (MPU)
  • User selectable Memory BIST
• Interrupts
  • 255 interrupt sources with 16 priority levels
  • Up to 54 ext. IRQ including 30 wake-up
• GPIOs: from 147 (QFP176) to 199 (BGA256)
• System timer units
  • 8-ch. 32-bit periodic interrupt timer (PIT)
  • 4-channel 32-bit system timer (STM)
  • Safety System Watchdog Timer (SWT)
  • Real-time clock timer (RTC/API)
• eMIOS, 16-bit counter timed I/O units
  • Up to 64 channels with PWM/MC/IC/OC
• Two ADC (10-bit and 12-bit)
  • Up to 62 channels extendable to 90 ch.
  • Multiple Analog Watchdog
• Dedicated diagnostic features for lighting
  • Advanced shifted PWM generation
  • ADC conversion synchronized on PWM
• Communication interfaces
  • Up to 6 FlexCAN with 64 buffers each
  • Up to 10 LINFlex/UART channels
  • Up to 8 buffered DSPI channels
  • I2 C interface
  • One FleyRay (dual-ch.) with 128 buffers
  • Fast Ethernet Controller
• Cryptographic Services Engine (CSE)
  • AES-128 en/decryption, CMAC auth.
  • Secured device boot mode
• 32-ch. eDMA with multiple request sources
• Clock generation
  • 4 to 40 MHz main oscillator
  • 16 MHz internal RC oscillator
  • Software-controlled FMPLL
  • 128 kHz internal RC oscillator
  • 32 kHz auxiliary oscillator
  • Clock Monitoring Unit (CMU)
• Low power capabilities
  • Ultra low power STANDBY
  • CAN Sampler to store CAN ID in STBY
  • Fast wake-up and execute from RAM
• Exhaustive debugging capability
  • Nexus 3+ interface on LBGA256 only
  • Nexus 1 on all devices
• Voltage supply
  • Single 5 V or 3.3 V supply
  • On-chip Vreg with external ballast transitor
• Operating temperature range -40 to 125 °C

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