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ST10F269：16Bit MCU 256K BYTE FLASH,12K BYTE RAM

The ST10F269 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL.

ST10F269 is processed in 0.35µm CMOS technology. The MCU core and the logic is supplied with a 5V to 3.3V on chip voltage regulator. The part is supplied with a single 5V supply and I/Os work at 5V.

The device is upward compatible with the ST10F168 device, with the following set of differences:The Multiply/Accumulate unit is available as standard. This MAC unit adds powerful DSP functions to the ST10 architecture, but maintains full compatibility for existing code.Flash control interface is now based on STMicroelectronics third generation of stand-alone Flash memories, with an embedded Erase/Program Controller. This completely frees up the CPU during programming or erasing the Flash.Two dedicated pins (DC1 and DC2) on the PQFP-144 package are used for decoupling the internally generated 3.3V core logic supply. Do not connect these two pins to 5.0V externalsupply. Instead, these pins should be connected to a decoupling capacitor (ceramic type, value 330 nF).The A/D Converter characteristics are different from previous ST10 derivatives ones. Refer to Section 21.3.1 - A/D Converter Characteristics.The AC and DC parameters are adapted to the 40MHz maximum CPU frequency. The characterization is performed with CL = 50pF max on output pins. Refer to Section 21.3 DC Characteristics.In order to reduce EMC, the rise/fall time and the sink/source capability of the drivers of the I/O pads are programmable. Refer to Section 12.2 I/Os Special Features.The Real Time Clock functionnality is added.The external interrupt sources can be selected with the EXISEL register.The reset source is identified by a dedicated status bit in the WDTCON register.

Key Features

• TWO CAN 2.0B INTERFACES OPERATING ON ONE OR TWO CAN BUSSES (30 OR 2x15 MESSAGE OBJECTS)
• SERIAL CHANNELSSYNCHRONOUS / ASYNCHRONOUS SERIAL CHANNELHIGH-SPEED SYNCHRONOUS CHANNEL
• ON-CHIP BOOTSTRAP LOADER
• FAIL-SAFE PROTECTIONPROGRAMMABLE WATCHDOG TIMEROSCILLATOR WATCHDOG
• REAL TIME CLOCK
• CLOCK GENERATIONON-CHIP PLLDIRECT OR PRESCALED CLOCK INPUT
• IDLE AND POWER DOWN MODES
• UP TO 111 GENERAL PURPOSE I/O LINESINDIVIDUALLY PROGRAMMABLE AS INPUT, OUTPUT OR SPECIAL FUNCTIONPROGRAMMABLE THRESHOLD (HYSTERESIS)
• SINGLE VOLTAGE SUPPLY: 5V ±10% (EMBEDDED REGULATOR FOR 3.3 V CORE SUPPLY).
• A/D CONVERTER16-CHANNEL 10-BIT4.85µs CONVERSION TIME AT 40MHz CPU CLOCK
• TWO 16-CHANNEL CAPTURE / COMPARE UNITS
• HIGH PERFORMANCE 40MHz CPU WITH DSP FUNCTION16-BIT CPU WITH 4-STAGE PIPELINE50ns INSTRUCTION CYCLE TIME AT 40MHz MAX CPU CLOCKMULTIPLY/ACCUMULATE UNIT (MAC) 16 x 16-BIT MULTIPLICATION, 40-BIT ACCUMULATOR REPEAT UNITENHANCED BOOLEAN BIT MANIPULATION FACILITIESADDITIONAL INSTRUCTIONS TO SUPPORT HLL AND OPERATING SYSTEMSSINGLE-CYCLE CONTEXT SWITCHING SUPPORT
• FAST AND FLEXIBLE BUSPROGRAMMABLE EXTERNAL BUS CHARACTERISTICS FOR DIFFERENT ADDRESS RANGES 8-BIT OR 16-BIT EXTERNAL DATA BUSMULTIPLEXED OR DEMULTIPLEXED EXTERNAL ADDRESS/DATA BUSES FIVE PROGRAMMABLE CHIP-SELECT SIGNALSHOLD-ACKNOWLEDGE BUS ARBITRATION SUPPORT
• MEMORY ORGANIZATION256K BYTE ON-CHIP FLASH MEMORY SINGLE VOLTAGE WITH ERASE/PROGRAM CONTROLLER.100K ERASING/PROGRAMMING CYCLES.UP TO 16M BYTE LINEAR ADDRESS SPACE FOR CODE AND DATA (5M BYTES WITH CAN)2K BYTE ON-CHIP INTERNAL RAM (IRAM) 10K BYTE ON-CHIP EXTENSION RAM (XRAM)
• TIMERS TWO MULTI-FUNCTIONAL GENERAL PURPOSE TIMER UNITS WITH 5 TIMERS
• 4-CHANNEL PWM UNIT
• 144-PIN PQFP PACKAGE
• INTERRUPT8-CHANNEL PERIPHERAL EVENT CONTROLLER FOR SINGLE CYCLE INTERRUPT DRIVEN DATA TRANSFER16-PRIORITY-LEVEL INTERRUPT SYSTEM WITH 56 SOURCES, SAMPLING RATE DOWN TO 25ns
• TEMPERATURE RANGE: -40 +125°C

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