技术参数参数 | 值 | Architecture | 16-bit | CPU Speed (MIPS) | 70 | Memory Type | Flash | Program Memory (KB) | 128 | RAM Bytes | 16,384 | Temperature Range C | -40 to 125 | Operating Voltage Range (V) | 3 to 3.6 | I/O Pins | 21 | Pin Count | 28 | System Management Features | BOR | POR | Yes | WDT | Yes | nanoWatt Features | Low Sleep/Fast Wake/Fast Control | Digital Communication Peripherals | 2-UART2-SPI2-I2C | Op Amp | 2 | Comparators | 3 | Capture/Compare/PWM Peripherals | 4/4 | PWM Resolution bits | 16 | Timers | 5 x 16-bit 2 x 32-bit | Parallel Port | GPIO | DMA | 4 | Cap Touch Channels | 6 |
Emulators & DebuggersDemo & Eval BoardsProgrammer | 技术特性- 3.0V to 3.6V, -40ºC to +85ºC, DC to 70 MIPS
- 3.0V to 3.6V, -40ºC to +125ºC, DC to 60 MIPS
- Modified Harvard Architecture
- C Compiler Optimized Instruction Set
- 16-bit Wide Data Path
- 24-bit Wide Instructions
- 16x16 Integer Multiply Operations
- 32/16 and 16/16 Integer Divide Operations
- ADC module:- Configurable as 10-bit, 1.1 Msps with four S&H or 12-bit, 500 ksps with one S&H
- Up to three Op amp/Comparators:- Op Amp direct connection to the ADC module- Additional dedicated comparator- Programmable references with 32 voltage points for comparators
- Charge Time Measurement Unit (CTMU):- Supports mTouch™ capacitive touch sensing
- 12 general purpose timers:- Five 16-bit and up to two 32-bit timers/counters- Four OC modules configurable as timers/counters- PTG module with two configurable timers/counters
- Four IC modules
- Peripheral Trigger Generator (PTG) for scheduling complex sequences
- Two UART modules (15 Mbps)
- Two 4-wire SPI modules (15 Mbps)
- Two I2C™ modules (up to 1 Mbaud) with SMBus support
- PPS to allow function remap
- Programmable Cyclic Redundancy Check (CRC)
- 4-channel DMA with user-selectable priority arbitration
- UART, SPI, ADC, IC, OC, and Timers
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