技术参数参数 | 值 | Architecture | 16-bit | CPU Speed (MIPS) | 40 | Memory Type | Flash | Program Memory (KB) | 12 | RAM Bytes | 1,024 | Temperature Range C | -40 to 125 | Operating Voltage Range (V) | 3 to 3.6 | I/O Pins | 13 | Pin Count | 20 | System Management Features | BOR | POR | Yes | WDT | Yes | Internal Oscillator | 7.37 MHz, 32.768 kHz | nanoWatt Features | Fast Wake/Fast Control | Digital Communication Peripherals | 1-UART1-SPI1-I2C | Analog Peripherals | 1-A/D 6x12-bit @ 500(ksps) | Capture/Compare/PWM Peripherals | 4/2 | PWM Resolution bits | 16 | Timers | 3 x 16-bit 1 x 32-bit | Parallel Port | GPIO | Cap Touch Channels | 6 |
Emulators & DebuggersDemo & Eval BoardsProgrammerSoftware & Compilers | Operating Range: - Up to 40 MIPS operation (@ 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
High-Performance CPU: - Modified Harvard architecture
- C compiler optimized instruction set
- 16-bit wide data path
- 24-bit wide instructions
- Linear program memory addressing up to 4M instruction words
- Linear data memory addressing up to 64 Kbytes
- 71 base instructions, mostly 1 word/1 cycle
- Sixteen 16-bit General Purpose Registers
- Flexible and powerful addressing modes
- Software stack
- 16 x 16 multiply operations
- 32/16 and 16/16 divide operations
- Up to ±16-bit shifts for up to 40-bit data
Interrupt Controller: - 5-cycle latency
- 118 interrupt vectors
- Up to 21 available interrupt sources
- Up to 3 external interrupts
- 7 programmable priority levels
- 4 processor exceptions
On-Chip Flash and SRAM: - Flash program memory (12 Kbytes)
- Data SRAM (1024 bytes)
- Boot and General Security for Program Flash
Digital I/O: - Peripheral Pin Select Functionality
- Up to 21 programmable digital I/O pins
- Wake-up/Interrupt-on-Change for up to 21 pins
- Output pins can drive from 3.0V to 3.6V
- Up to 5V output with open drain configuration
- All digital input pins are 5V tolerant
- 4 mA sink on all I/O pins
System Management: - Flexible clock options:
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
- Power-up Timer
- Oscillator Start-up Timer/Stabilizer
- Watchdog Timer with its own RC oscillator
- Fail-Safe Clock Monitor
- Reset by multiple sources
Power Management: - On-chip 2.5V voltage regulator
- Switch between clock sources in real time
- Idle, Sleep and Doze modes with fast wake-up
Timers/Capture/Compare: - Timer/Counters, up to three 16-bit timers:
- Can pair up to make one 32-bit timer
- 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator
- Programmable prescaler
- Input Capture (up to 4 channels):
- Capture on up, down or both edges
- 16-bit capture input functions
- 4-deep FIFO on each capture
- Output Compare (up to 2 channels):
- Single or Dual 16-Bit Compare mode
- 16-bit Glitchless PWM Mode
Communication Modules: - 4-wire SPI
- Framing supports I/O interface to simple codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and sampling modes
- I2C™
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
- UART
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
Analog-to-Digital Converters (ADCs): - 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:
- 2 and 4 simultaneous samples (10-bit ADC)
- Up to 10 input channels with auto-scanning
- Conversion start can be manual or synchronized with 1 of 4 trigger sources
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
CMOS Flash Technology: - Low-power, high-speed Flash technology
- Fully static design
- 3.3V (±10%) operating voltage
- Industrial and extended temperature
- Low-power consumption
Packaging: |