MC100E210: 5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout Buffer

The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part-to-part skew down to an output-to-output skew. This capability reduces the skew by a factor of 4 as compared to using twoLVE111's to accomplish the same task.The lowest tpd delay time results from terminating only one output pair, and the greatest tpd delay time results from terminating all the output pairs. This shift is about 10-20 pS in tpd. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest tpd delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest tpd (delay time) occurs and all outputs display about the same 10-20 pS increase in tpd, so the relative skew between any two output pairs remains about 25 nS.For more information on using PECL, designers should refer to Application Note AN1406/D.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性
  • Dual Differential Fanout Buffers
  • 200 ps Part-to-Part Skew
  • 50 ps Typical Output-to-Output Skew
  • Low Voltage ECL/PECL Compatible
  • The 100 Series Contains Temperature Compensation
  • 28-lead PLCC Packaging
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = ?4.2 V to ?5.7 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • Q Output will Default LOW with Inputs Open or at VEE
  • ESD Protection: >2KV HBM, >200V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8?, Oxygen Index 28 to 34
  • Transistor Count = 179 devices
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS™ Circuit Performance at Non-Standard VIH LevelsAN1404/D (51.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL Dual 1:4, 1:5 Differential Fanout BufferMC100E210/D (117.0kB)3
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100e210fn -5.2VMC100E210FN_-52.IBS (8.0kB)1.0
封装图纸 (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价)
MC100E210FNGActivePb-free Halide free5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout BufferPLCC-28776-023Tube37联系BDTIC
MC100E210FNR2GActivePb-free Halide free5.0 V ECL Dual 1:4, 1:5 Differential Clock/Data Fanout BufferPLCC-28776-023Tape and Reel500联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100E210FNGBuffer21:4   1:5ECLECL5<1750.6600700
MC100E210FNR2GBuffer21:4   1:5ECLECL5<1750.6600700
5V ECL Dual 1:4, 1:5 Differential Fanout Buffer MC100E210
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS™ Circuit Performance at Non-Standard VIH Levels MC10E195
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100e210fn -5.2V MC100E210
28 LEAD PLCC MC10H604