MC100EL29: 5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and Reset

The MC100EL29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.

特性
  • 1100 MHz Flip-Flop Toggle Frequency
  • 580 ps Propagation Delays
  • ESD Protection: > 2 kV HBM, > 100 V MM
  • Q Output will Default LOW with Inputs Open or at VEE
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors on D(s), CLK(s), S(s), and R(s).
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Flammability Rating: UL-94 code V-0 @ 0.125 in, Oxygen Index 28 to 34
  • Transistor Count = 313 devices
  • Pb-Free Packages are Available
应用注释 (17)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS and ECLinPS Lite SPICE I/O Modeling KitAN1503/D (120.0kB)6
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (66kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and ResetMC100EL29/D (116.0kB)4
仿真模型 (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS model for mc100el29dw VEE at -5.0 VMC100EL29DW_-50.IBS (9.0kB)1
封装图纸 (1)
Document TitleDocument ID/SizeRevision
SOIC-20 WB751D-05 (36.3kB)H
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价)
MC100EL29DWGActivePb-free Halide free5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and ResetSOIC-20W751D-053Tube38联系BDTIC
MC100EL29DWR2GActivePb-free Halide free5.0 V ECL Dual Differential Clock / Data D Flip-Flop With Set and ResetSOIC-20W751D-053Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC100EL29DWGD-Type2ECL   LVDSECL510.600.10.15501100
MC100EL29DWR2GD-Type2ECL   LVDSECL510.600.10.15501100
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset MC100EL29
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit MC100EP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS model for mc100el29dw VEE at -5.0 V MC100EL29
SOIC-20 WB NLSX3018