MC100LVEL05: ECL 2-Input Differential AND/NAND Gate

The MC100LVEL05 is a 2-input differential AND/NAND gate. The device is functionally equivalent to the MC100EL05 device and operates from a 3.3V supply voltage. With propagation delays and output transition times equivalent to the EL05, the LVEL05 is ideally suited for those applications which require the ultimate in AC performance at low voltage power supplies. Because a negative 2-input NAND is equivalent to a 2-input OR function, the differential inputs and outputs of the device allows the LVEL05 to also be used as a 2-input differential OR/NOR gate.

特性
  • 340ps Propagation Delay
  • High Bandwidth Output Transitions
  • ESD Protection: >4 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Q Output will Default LOW with All Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 69 devices
  • Pb-Free Packages are Available
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (66kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V ECL 2-Input Differential AND/NANDMC100LVEL05/D (132.0kB)4
仿真模型 (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100lvel05dMC100LVEL05D_33.IBS (5.0kB)2
IBIS Model for mc100lvel05dtMC100LVEL05DT_33.IBS (5.0kB)1
Low Voltage ECLinPS SPICE Modeling KitAN1560/D (88.0kB)5
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价）
MC100LVEL05DGActivePb-free Halide freeECL 2-Input Differential AND/NAND GateSOIC-8751-071Tube98联系BDTIC
MC100LVEL05DR2GActivePb-free Halide freeECL 2-Input Differential AND/NAND GateSOIC-8751-071Tape and Reel2500联系BDTIC
MC100LVEL05DTGActivePb-free Halide freeECL 2-Input Differential AND/NAND GateTSSOP-8948R-023Tube100联系BDTIC
MC100LVEL05DTR2GActivePb-free Halide freeECL 2-Input Differential AND/NAND GateTSSOP-8948R-023Tape and Reel2500联系BDTIC
订购产品技术参数
ProductTypeChannelsInput LevelOutput LevelVCC Typ (V)fToggle Max (MHz)tpd Typ (ns)tJitter Typ (ps)tR & tF Max (ps)
MC100LVEL05DGAND/NAND1ECL   LVDSECL3.320000.341320
MC100LVEL05DR2GAND/NAND1ECL   LVDSECL3.320000.341320
MC100LVEL05DTGAND/NAND1ECL   LVDSECL3.320000.341320
MC100LVEL05DTR2GAND/NAND1ECL   LVDSECL3.320000.341320
3.3 V ECL 2-Input Differential AND/NAND (163kB) MC100LVEL05
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100lvel05d MC100LVEL05
IBIS Model for mc100lvel05dt MC100LVEL05
Low Voltage ECLinPS SPICE Modeling Kit MC100LVELT23
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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