MC100LVEL37: Clock / Data Fanout Buffer, 1:4 Differential, ÷1 / ÷2, 3.3 V

The MC100LVEL37 is a fully differential 1:4 fanout buffer. The device offers two outputs at 1 of the input frequency, and two outputs at 2 of the input frequency. The Low Output-Output Skew of the device makes it ideal for distributing 1x and 1/2x frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the CLKn input will pull down to VEE. The CLKnbar input will bias around VCC/2 and the Qn output will go LOW.

特性

700ps Typical Propagation Delays
50 ps Maximum Output-Output Skews
ESD Protection: >2 KV HBM, >200 V MM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
Internal Input Pulldown Resistors
Qn Output will Default LOW with Inputs Open or at VEE
Qn Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 256 devices
Pb-Free Packages are Available

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V ECL 1:4 ÷1 / ÷2 Clock Fanout Buffer	MC100LVEL37/D (146kB)	7	Jul, 2016

仿真模型 (2)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for mc100lvel37dw 3.3V	MC100LVEL37DW_33.IBS (10.0kB)	2
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5

封装图纸 (1)

Document Title	Document ID/Size	Revision
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100LVEL37DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
MC100LVEL37DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC