MC100LVEP11: ECL 1:2 Differential Clock / Data Fanout Buffer

The MC10LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single ended CLK input operation is limited to a VCC >= 3.0 V in PECL mode, or VEE <= -3.0 V in NECL mode.The 100 Series contains temperature compensation.

特性
  • 240 ps Typical Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -2.375 V to -3.8 V
  • Open Input Default State
  • Q Outputs will default LOW with inputs open or at VEE
  • LVDS Input Compatible
应用
  • GbE or Fibre Channel Redundant Fan-out
封装
应用注释 (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V / 3.3 V ECL 1:2 Differential Fanout BufferMC10LVEP11/D (243kB)14Aug, 2016
仿真模型 (3)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC100LVEP11D at 3.3VMC100LVEP11D_33V.IBS (5.0kB)2
IBIS Model for mc100lvep11dt 2.5VMC100LVEP11DT_25.IBS (5.0kB)3
IBIS Model for mc100lvep11dt 3.3VMC100LVEP11DT_33.IBS (6.0kB)2
封装图纸 (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC100LVEP11DGActivePb-free Halide freeSOIC-8751-071Tube98联系BDTIC
MC100LVEP11DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500联系BDTIC
MC100LVEP11DTGActivePb-free Halide freeTSSOP-8948R-023Tube100联系BDTIC
MC100LVEP11DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500联系BDTIC
MC100LVEP11MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000联系BDTIC
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
MC100LVEP11DGBuffer11:2ECL CML LVDSECL3.3 2.51.42200.241703000
MC100LVEP11DR2GBuffer11:2LVDS CML ECLECL2.5 3.31.42200.241703000
MC100LVEP11DTGBuffer11:2LVDS CML ECLECL3.3 2.51.42200.241703000
MC100LVEP11DTR2GBuffer11:2CML ECL LVDSECL3.3 2.51.42200.241703000
MC100LVEP11MNR4GBuffer11:2CML LVDS ECLECL2.5 3.31.42200.241703000
2.5 V / 3.3 V ECL 1:2 Differential Fanout Buffer (243kB) MC10LVEP11
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC100LVEP11D at 3.3V MC100LVEP11
IBIS Model for mc100lvep11dt 2.5V MC100LVEP11
IBIS Model for mc100lvep11dt 3.3V MC100LVEP11
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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