MC100LVEP14: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer
The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
特性
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封装
应用注释 (15)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
| Designing with PECL (ECL at +5.0 V) | AN1406/D (105.0kB) | 2 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| ECLinPS Plus™ Spice Modeling Kit | AND8009/D (343.0kB) | 11 | |
| ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide | AND8002 (71kB) | 12 | |
| Interfacing Between LVDS and ECL | AN1568/D (121.0kB) | 11 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Phase Lock Loop General Operations | AND8040/D (64.0kB) | 3 | |
| Storage and Handling of Drypack Surface Mount Device | AND8003/D (49kB) | 2 | Mar, 2016 |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 | |
| Thermal Analysis and Reliability of WIRE BONDED ECL | AND8072/D (119.0kB) | 5 | |
| Using Wire-OR Ties in ECLInPS™ Designs | AN1650/D (1130.0kB) | 3 |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver | MC100LVEP14/D (90kB) | 14 |
仿真模型 (3)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| ECLinPS Plus SPICE Modeling Kit | AND8009 (343.0kB) | 11 | |
| IBIS Model for MC100LVEP14DT 2.5V | MC100LVEP14DT_25.IBS (9.0kB) | 3 | |
| IBIS Model for MC100LVEP14DT 3.3V | MC100LVEP14DT_33.IBS (10.0kB) | 2 |
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| TSSOP-20 WB | 948E-02 (39.7kB) | D |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100LVEP14DTG | Active | Pb-free Halide free | TSSOP-20 | 948E-02 | 1 | Tube | 75 | 联系BDTIC |
| MC100LVEP14DTR2G | Active | Pb-free Halide free | TSSOP-20 | 948E-02 | 1 | Tape and Reel | 2500 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MC100LVEP14DTG | Buffer | 1 | 2:1:5 | HSTL CML ECL LVDS | ECL | 2.5 3.3 | 0.181 | 25 | 0.4 | 225 | 2000 | |
| MC100LVEP14DTR2G | Buffer | 1 | 2:1:5 | LVDS HSTL CML ECL | ECL | 3.3 2.5 | 0.181 | 25 | 0.4 | 225 | 2000 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- ECLinPS Plus SPICE Modeling Kit NB4N840M
- IBIS Model for MC100LVEP14DT 2.5V MC100LVEP14
- IBIS Model for MC100LVEP14DT 3.3V MC100LVEP14
- TSSOP-20 WB NLSX3018
