MC10H645: 2:1:9 TTL Clock Driver _ BDTIC 中国领先电子元器件代理商

MC10H645: 2:1:9 TTL Clock Driver

The MC10H645 is a single supply, low skew, TTL I/O 2:1:9 Clock Driver. Devices in the Motorola H600 clock driver family utiize the 28-lead PLCC for optimal power and signal pin placement. The device features a 24mA TTL ouput stage with AC performance specified into a 50pF load capacitance. A 2:1 input mux is provided on chip to allow for distributing both system and diagnostic clock signals or designing clock redundancy into a system. With the SEL input held LOW the DO input will be selected, while the D1 input is selected when the SEL input is forced HIGH.

特性

Low Skew Typically 0.65ns Within Device
Guaranteed Skew Spec 1.25ns Part-to-Part
Input Clock Muxing
Differential ECL Internal Design
Single Supply
Extra TTL and ECL Power/Ground Pins
Pb-Free Packages are Available

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Family Characteristics for MECL 10H™ and MECL 10K™	TND309/D (248.0kB)	1
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5