NB6L16: Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL

The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With output transition times of 70 ps, it is ideally suited for high frequency, low power systems. The device is targeted for Backplane buffering, GbE clock/data distribution, Fibre Channel distribution and SONET clock/data distribution applications.Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals.The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

Input Clock Frequency 6 GHz
Input Data Rate Frequency 6 Gb/s
Low 12 mA Typical Power Supply Current
70 ps Typical Rise/Fall Times
130 ps Input Propagation Delay
On-Chip Reference for ECL Single-Ended Input - VBB Output
PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 with VEE = 2.375 V to 3.465 V
Open Input Default State
LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input Compatible
Low-power Clock Buffering for Power constrained PC Add-on cards

应用

Backplane Data buffering
Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Max (SiGe) SPICE Modeling Kit	AND8157/D (129.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL	NB6L16/D (261kB)	9	Aug, 2016

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for nb6l16d (2.5V and 3.3V)	NB6L16D.IBS (35.0kB)	1

封装图纸 (2)

Document Title	Document ID/Size	Revision
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB6L16DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
NB6L16DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
NB6L16DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
NB6L16DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)	fmaxData Typ (Mbps)
NB6L16DG	Signal Driver	1	1:1	TTL LVDS ECL CML CMOS	ECL	3.3 2.5	0.2	0.13	120	6000	6000
NB6L16DR2G	Signal Driver	1	1:1	CML ECL LVDS TTL CMOS	ECL	3.3 2.5	0.2	0.13	120	6000	6000
NB6L16DTG	Signal Driver	1	1:1	CML TTL LVDS CMOS ECL	ECL	2.5 3.3	0.2	0.13	120	6000	6000
NB6L16DTR2G	Signal Driver	1	1:1	TTL CML CMOS LVDS ECL	ECL	2.5 3.3	0.2	0.13	120	6000	6000