M24M01-W 1Mb串行I²C总线的EEPROM
The M24M01-R, M24M01-HR and M24M01-W are I²C-compatible electrically erasable programmable memory (EEPROM) devices organized as 128 Kb × 8 bits.
The I²C bus is a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I²C bus definition.
The M24M01-R, M24M01-HR and M24M01-W behave as slaves in the I²C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are generated by the bus master and initiated by a Start condition, followed by the device select code, address bytes and data bytes. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way
M24M01-W 特性:
- Compatible with I²C extended addressing
- Two-wire I²C serial interface:
– M24M01-HR:1 MHz clock, compatible with the Fastmode Plus I²C protocol
– M24M01-R, M24M01-W: 400 kHz clock, compatible with the Fastmode I²C protocol - Single supply voltage:
– 1.8 V to 5.5 V
– 2.5 V to 5.5 V - Hardware write control
- Byte and Page Write (up to 256 bytes)
- Random and Sequential Read modes
- Self-timed programming cycle
- Automatic address incrementing
- Enhanced ESD/Latch-Up protection
- More than 1 million Write cycles
- More than 40-year data retention
- Packages
– ECOPACK? (RoHS compliant)
M24M01-W 技术支持与电子电路设计开发资源下载
- M24M01-W 数据手册DataSheet下载.PDF
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