54AC11074 具有清零和预设功能的双路上升沿 D 类触发器

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () input sets or resets the outputs regardless of the levels of the other inputs. When and are inactive (high), data at the data (D) input that meets the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input may be changed without affecting the levels at the outputs.

The 54AC11074 is characterized for operation from -40°C to 85°C

54AC11074
Voltage Nodes(V) 5, 3.3  
Vcc range(V) 3.0 to 5.5  
Input Level CMOS  
Output Level CMOS  
Output Drive(mA) -24/24  
Output 3S  
No. of Bits 2  
Static Current 0.04  
th(ns) 0  
tpd max(ns) 8.2  
tsu(ns) 3.5  
Technology Family AC  
Rating Catalog
54AC11074 特性
54AC11074 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
54AC11074D ACTIVE -40 to 85 1.60 | 1ku SOIC (D) | 14 50 | TUBE  
54AC11074DE4 ACTIVE -40 to 85 1.60 | 1ku SOIC (D) | 14 50 | TUBE  
54AC11074DG4 ACTIVE -40 to 85 1.60 | 1ku SOIC (D) | 14 50 | TUBE  
54AC11074DR ACTIVE -40 to 85 1.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R  
54AC11074DRE4 ACTIVE -40 to 85 1.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R  
54AC11074DRG4 ACTIVE -40 to 85 1.35 | 1ku SOIC (D) | 14 2500 | LARGE T&R  
54AC11074N ACTIVE -40 to 85 1.45 | 1ku PDIP (N) | 14 25 | TUBE  
54AC11074NE4 ACTIVE -40 to 85 1.45 | 1ku PDIP (N) | 14 25 | TUBE  
54AC11074PWLE OBSOLETE -40 to 85   TSSOP (PW) | 14    
54AC11074PWR ACTIVE -40 to 85 1.35 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R  
54AC11074PWRE4 ACTIVE -40 to 85 1.35 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R  
54AC11074PWRG4 ACTIVE -40 to 85 1.35 | 1ku TSSOP (PW) | 14 2000 | LARGE T&R  
54AC11074 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
54AC11074D Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074D 54AC11074D
54AC11074DE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074DE4 54AC11074DE4
54AC11074DG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074DG4 54AC11074DG4
54AC11074DR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074DR 54AC11074DR
54AC11074DRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074DRE4 54AC11074DRE4
54AC11074DRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074DRG4 54AC11074DRG4
54AC11074N Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type 54AC11074N 54AC11074N
54AC11074NE4 Pb-Free (RoHS)  CU NIPDAU  N/A for Pkg Type 54AC11074NE4 54AC11074NE4
54AC11074PWR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074PWR 54AC11074PWR
54AC11074PWRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074PWRE4 54AC11074PWRE4
54AC11074PWRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM 54AC11074PWRG4 54AC11074PWRG4
54AC11074 应用技术支持与电子电路设计开发资源下载
  1. 54AC11074 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)