SN54ABT18502 具有 18 位寄存总线收发器的扫描测试设备

The SN54ABT18502 scan test device with 18-bit universal bus transceiver is a member of the Texas Instruments SCOPETM testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells

	SN54ABT18502
Voltage Nodes (V)	5
Technology Family	ABT
Rating	Military

SN54ABT18502 特性

Member of the Texas Instruments SCOPETM Family of Testability Products
Member of the Texas Instruments WidebusTM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
Two Boundary-Scan Cells per I/O for Greater Flexibility
State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
Packaged in 68-Pin Ceramic Quad Flat Package Using 25-mil Center-to-Center Spacings

SN54ABT18502 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
5962-9467201QXA	ACTIVE	-55 to 125	98.22 \| 1ku	CFP (HV) \| 68	1 \| TUBE
SNJ54ABT18502HV	ACTIVE	-55 to 125	98.22 \| 1ku	CFP (HV) \| 68	1 \| TUBE

SN54ABT18502 应用手册

标题	类型	大小
选择合适的德州仪器 (TI) 信号开关	PDF	1091
Shelf-Life Evaluation of Lead-Free Component Finishes	PDF	1310
Understanding and Interpreting Standard-Logic Data Sheets	PDF	857
TI IBIS File Creation, Validation, and Distribution Processes	PDF	380
Implications of Slow or Floating CMOS Inputs	PDF	101
CMOS Power Consumption and CPD Calculation	PDF	89
Designing With Logic	PDF	186
Live Insertion	PDF	150
Input and Output Characteristics of Digital Integrated Circuits	PDF	1708
SN54/74HCT CMOS Logic Family Applications and Restrictions	PDF	102
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc	PDF	43

SN54ABT18502 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
5962-9467201QXA	TBD	Call TI	Call TI	5962-9467201QXA	5962-9467201QXA
SNJ54ABT18502HV	TBD	Call TI	N/A for Pkg Type	SNJ54ABT18502HV	SNJ54ABT18502HV

SN54ABT18502 应用技术支持与电子电路设计开发资源下载

SN54ABT18502 数据资料 dataSheet 下载.PDF
TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
CMOS Power Consumption and CPD Calculation (PDF 89 KB)
Designing With Logic (PDF 186 KB)
Live Insertion (PDF 150 KB)
Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
HiRel Unitrode Power Management Brochure (PDF 206 KB)
LOGIC Pocket Data Book (PDF 6001 KB)
HiRel Unitrode Power Management Brochure (PDF 206 KB)
Logic Cross-Reference (PDF 2938 KB)