SN54ABT8543 具有八路寄存总线收发器的扫描测试设备
The 'ABT8543 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F543 and 'ABT543 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers
|
SN54ABT8543 |
| Voltage Nodes(V) |
5 |
| Vcc range(V) |
4.5 to 5.5 |
| Input Level |
TTL |
| Logic |
True |
| No. of Outputs |
8 |
| Output Drive(mA) |
-32/54 |
| tpd max(ns) |
5.5 |
| Output Level |
TTL |
| Static Current |
20 |
| Rating |
Military |
| Technology Family |
ABT |
SN54ABT8543 特性
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- Functionally Equivalent to 'F543 and 'ABT543 in the Normal-Function Mode
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
- Parallel-Signature Analysis at Inputs With Masking Option
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Even-Parity Opcodes
- Two Boundary-Scan Cells Per I/O for Greater Flexibility
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DL) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)
SN54ABT8543 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 5962-9461501Q3A |
ACTIVE |
-55 to 125 |
43.64 | 1ku |
LCCC (FK) | 28 |
1 | TUBE |
|
| 5962-9461501QXA |
ACTIVE |
-55 to 125 |
28.02 | 1ku |
CDIP (JT) | 28 |
1 | TUBE |
|
| SNJ54ABT8543FK |
ACTIVE |
-55 to 125 |
43.64 | 1ku |
LCCC (FK) | 28 |
1 | TUBE |
|
| SNJ54ABT8543JT |
ACTIVE |
-55 to 125 |
28.02 | 1ku |
CDIP (JT) | 28 |
1 | TUBE |
|
SN54ABT8543 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 5962-9461501Q3A |
TBD |
POST-PLATE |
N/A for Pkg Type |
5962-9461501Q3A |
5962-9461501Q3A |
| 5962-9461501QXA |
TBD |
A42 |
N/A for Pkg Type |
5962-9461501QXA |
5962-9461501QXA |
| SNJ54ABT8543FK |
TBD |
POST-PLATE |
N/A for Pkg Type |
SNJ54ABT8543FK |
SNJ54ABT8543FK |
| SNJ54ABT8543JT |
TBD |
A42 |
N/A for Pkg Type |
SNJ54ABT8543JT |
SNJ54ABT8543JT |
SN54ABT8543 应用技术支持与电子电路设计开发资源下载
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
