SN54ABTH18646A 具有 18 位收发器和寄存器的扫描测试设备

The 'ABTH18646A and 'ABTH182646A scan test devices with 18-bit bus transceivers and registers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit bus transceivers and registers that allow for multiplexed transmission of data directly from the input bus or from the internal registers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells

	SN54ABTH18646A
Voltage Nodes (V)	5
Vcc range (V)	4.5 to 5.5
Input Level	TTL
Output Level	TTL
No. of Outputs	18
Logic	True
Technology Family	ABT
Rating	Military

SN54ABTH18646A 特性

Members of the Texas Instruments SCOPETM Family of Testability Products
Members of the Texas Instruments WidebusTM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data
Bus Hold on Data Inputs Eliminates the Need for External Pullup Resistors
B-Port Outputs of 'ABTH182646A Devices Have Equivalent 25- Series Resistors, So No External Resistors Are Required
State-of-the-Art EPIC-IIBTM BiCMOS Design
One Boundary-Scan Cell Per I/O Architecture Improves Scan Efficiency
SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin Ceramic Quad Flat (HV) Packages Using 25-mil Center-to-Center Spacings

SN54ABTH18646A 芯片订购指南

器件	状态	温度	价格（美元）	封装 \| 引脚	封装数量 \| 封装载体	丝印标记
5962-9669801QXA	ACTIVE	-55 to 125	48.68 \| 1ku	CFP (HV) \| 68	1 \| TUBE
SNJ54ABTH18646AHV	ACTIVE	-55 to 125	48.68 \| 1ku	CFP (HV) \| 68	1 \| TUBE

SN54ABTH18646A 应用手册

标题	类型	大小
选择正确的电平转换解决方案 (Rev. A)	PDF	635
Shelf-Life Evaluation of Lead-Free Component Finishes	PDF	1310
Quad Flatpack No-Lead Logic Packages	PDF	1048
Understanding and Interpreting Standard-Logic Data Sheets	PDF	857
TI IBIS File Creation, Validation, and Distribution Processes	PDF	380
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	PDF	209
Implications of Slow or Floating CMOS Inputs	PDF	101
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs	PDF	105
Advanced BiCMOS Technology (ABT) Logic Characterization Information	PDF	528
Designing With Logic	PDF	186
Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design	PDF	115
Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices	PDF	80
Live Insertion	PDF	150
Input and Output Characteristics of Digital Integrated Circuits	PDF	1708
Understanding Advanced Bus-Interface Products Design Guide	PDF	253

SN54ABTH18646A 质量与无铅数据

器件	环保计划*	铅/焊球涂层	MSL 等级/回流焊峰	环保信息与无铅 (Pb-free)	DPPM / MTBF / FIT 率
5962-9669801QXA	TBD	Call TI	Call TI	5962-9669801QXA	5962-9669801QXA
SNJ54ABTH18646AHV	TBD	Call TI	N/A for Pkg Type	SNJ54ABTH18646AHV	SNJ54ABTH18646AHV