SN54LS73A 具有清零功能和三态输出的双路 J-K 触发器
The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C
| SN54LS73A | |
| Voltage Nodes(V) | 5 |
| Rating | Military |
SN54LS73A 特性
- Package Options Include Plastic “Small Outline" Packages, Flat Packages, and Plastic and Ceramic DIPs
- Dependable Texas Instruments Quality and Reliability
SN54LS73A 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54LS73AFD | ACTIVE | -55 to 125 | 9.75 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS73AJ | ACTIVE | -55 to 125 | 5.95 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54LS73AWD | ACTIVE | -55 to 125 | 10.35 | 1ku | CFP (W) | 14 | 1 | TUBE |
SN54LS73A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54LS73AFD | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS73AFD | SNJ54LS73AFD |
| SNJ54LS73AJ | TBD | A42 | N/A for Pkg Type | SNJ54LS73AJ | SNJ54LS73AJ |
| SNJ54LS73AWD | TBD | Call TI | N/A for Pkg Type | SNJ54LS73AWD | SNJ54LS73AWD |
SN54LS73A 应用技术支持与电子电路设计开发资源下载
- SN54LS73A 数据资料 dataSheet 下载.PDF
- TI 德州仪器触发器/锁存器/寄存器产品选型与价格 . xls
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